JPS63138467A - Wiring processing system - Google Patents

Wiring processing system

Info

Publication number
JPS63138467A
JPS63138467A JP61284159A JP28415986A JPS63138467A JP S63138467 A JPS63138467 A JP S63138467A JP 61284159 A JP61284159 A JP 61284159A JP 28415986 A JP28415986 A JP 28415986A JP S63138467 A JPS63138467 A JP S63138467A
Authority
JP
Japan
Prior art keywords
wiring
area
grating
data
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61284159A
Other languages
Japanese (ja)
Inventor
Shinichi Asami
阿左美 眞一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61284159A priority Critical patent/JPS63138467A/en
Publication of JPS63138467A publication Critical patent/JPS63138467A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To process in real time a wiring job of a large-scale/multi-layer substrate having high density by dividing a substrate into areas and forming a wiring section over these divided areas in 1/N (N>=1) of an allowable wiring grating. CONSTITUTION:A wiring job is carried out between two points connected to each other in a wiring design mode by setting a wiring grating for wiring processing on a substrate. In this case, the substrate is divided into an optional number of areas by an area dividing means 4. An inter-area wiring means 5 uses only the wiring grating of 1/N (N>=1) allowable wiring grating to perform a wiring job for section among those divided areas. An intra-area wiring means 6 performs wiring jobs in wiring sections in each area by means of the allowable wiring grating. In such a constitution, the handling data quantity is never limited and the wiring processing can be attained in real time with a large-scale/multi- layer substrate having high density despite increase of the number of wiring sections and wiring gratings.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はプリント配線板、セラミック配線板などの配
線設計における配線処理方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wiring processing method in wiring design for printed wiring boards, ceramic wiring boards, and the like.

〔従来の技術〕[Conventional technology]

従来、この種の配線処理方式は、基板上に配線処理用の
配線格子を設定し各結線すべき2点間(以下配線区間と
言う)の配線処理を基板全体で行なうものであった。
Conventionally, in this type of wiring processing method, a wiring grid for wiring processing is set on a board, and wiring processing between two points to be connected (hereinafter referred to as a wiring section) is performed on the entire board.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の配線処理方式は、近年の高密度。 The conventional wiring processing method mentioned above has become more dense in recent years.

高多層および大規模化基板の配線処理の場合には配線区
間数や配線格子数の増大によシ取シ扱えるデータ量の規
模的制約から配線処理ができない、あるいは配線処理が
実時間で終了しないなどという欠点があった。
In the case of wiring processing for highly multi-layered and large-scale boards, due to the increase in the number of wiring sections and wiring grids, wiring processing cannot be performed due to scale constraints on the amount of data that can be handled, or wiring processing cannot be completed in real time. There were some drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

この発明の配線処理方式は、基板を領域分割し、領域間
Kまたがる配線区間を許容配線格子の1/N(ただしN
≧1)に設定し処理するものである。
The wiring processing method of the present invention divides the board into regions, and divides the wiring section spanning K between the regions to 1/N (however, N
≧1).

〔作用〕[Effect]

この発明は高密度、高多層および大規模化基板の配線処
理を実時間で処理することができる。
The present invention can perform wiring processing for high-density, high-multilayer, and large-scale boards in real time.

〔実施例〕〔Example〕

図はこの発明に係る配線処理方式の一実施例を示すブロ
ック図である。同図において、1および2は配線処理の
入力となる配線区間および基板サイズ、層数、各種配線
禁止、最小配線格子などの配線区間データおよび障害デ
ータ、3は分割配線処理を行なうときの制御データであ
る分割指示データ、4は基板を任意の数に領域分割する
領域分割手段、5は各領域間にまたがる配線区間の配線
を許容配線格子の1/N(ただしN≧1)の配線格子の
みを使用して配線する領域間配線手段、6は各領域内の
配線区間の配線を許容配線格子を使用して、各領域単位
に配線する領域内配線手段、Tは配線処理の出力であシ
、各配線区間に対する配線軸路を示す配線データである
The figure is a block diagram showing an embodiment of the wiring processing method according to the present invention. In the figure, 1 and 2 are wiring section data and fault data such as wiring section, board size, number of layers, various wiring prohibitions, minimum wiring grid, etc. that are input for wiring processing, and 3 is control data when performing split wiring processing. division instruction data, 4 is a region dividing means for dividing the board into an arbitrary number of regions, and 5 is only a wiring grid of 1/N (however, N≧1) of the wiring grid that allows wiring in the wiring section spanning between each region. 6 is an intra-region wiring means for wiring the wiring sections in each region in units of each region using an allowable wiring grid; T is the output of the wiring process; , is wiring data indicating a wiring axis path for each wiring section.

次に、上記構成による配線処理方式の動作について説明
する。まず、領域分割手段4は制御データである分割指
示データ3に従って、配線区間データ1および障害デー
タ2を分割領域単位に分類する。このとき、領域間にま
たがる配線区間データはそれだけを1つの分類とし、゛
この領域間にまたがる配線区間の配線処理の際、使用す
る配線格子を許容配線格子の1/N(ただしN≧1)に
するための配線格子変換指示データを分割指示データ3
よシ得て、領域間配線処理で使用する配線格子に関係す
る障害データも1つの分類とする。次に、領域間配線手
段5は領域分割手段4で分類されたデータの中から領域
間配線区間および対応する障害データのみを対象として
、配線格子変換指示データで示される配線格子だけを使
用して、領域間にまたがる配線区間の配線処理を行なう
。この配線区間に対する配線峰路データは配線データT
に出力する。そして、求められた配給経路データを分割
領域単位に分類し、各領域単位に分類されている障害デ
ータに新たな障害データとして付は加えておく。次に、
領域内配線手段6は領域分割手段4で分類された残シの
データ、すなわち各領域内配線区間および対応する障害
データを対象として、各領域単位に領域内の配線区間の
配線処理を、許容配線格子を使用して行う。そして、配
線区間に対する配線経路データを配線データTに出力す
ることによ)、配線処理を実時間で行なうことができる
Next, the operation of the wiring processing method with the above configuration will be explained. First, the region dividing means 4 classifies the wiring section data 1 and the fault data 2 into divided regions according to the division instruction data 3 which is control data. At this time, the wiring section data that spans between areas is classified into one category, and the wiring grid used when wiring the wiring section that spans between these areas is set to 1/N of the allowable wiring grid (however, N≧1). Divide the wiring grid conversion instruction data to
For this reason, failure data related to the wiring grid used in inter-area wiring processing is also classified into one category. Next, the inter-area wiring means 5 targets only the inter-area wiring sections and the corresponding failure data from the data classified by the area dividing means 4, using only the wiring grid indicated by the wiring grid conversion instruction data. , performs wiring processing for wiring sections spanning between regions. The wiring peak road data for this wiring section is the wiring data T
Output to. The obtained distribution route data is then classified into divided areas, and new failure data is added to the failure data classified into each area. next,
The intra-area wiring means 6 targets the remaining data classified by the area dividing means 4, that is, each intra-area wiring section and the corresponding failure data, and performs wiring processing on the intra-area wiring sections for each area, and determines the permissible wiring. Do this using a grid. Then, by outputting the wiring route data for the wiring section as the wiring data T), wiring processing can be performed in real time.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、この発明に係る配線処理方
式によれば、基板を領域分割し、領域間Kまたがる配線
区間を許容配線格子の1/N(ただしN≧1)で行なう
ことによシ、大規模、高多層。
As explained in detail above, according to the wiring processing method according to the present invention, the board is divided into regions, and the wiring section spanning K between the regions is performed at 1/N (however, N≧1) of the allowable wiring grid. Large scale, high multilayer.

高密度基板の配線処理を実時間で処理することができる
効果がある。
This has the effect of making it possible to process wiring on high-density boards in real time.

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの発明に係る配線処理方式の一実施例を示すブロ
ック図である。 1・・・−配線区間データ、2e・・・障害データ、3
・・・・分割指持データ、4・・・・領域分割手段、5
・・・・領域間配線手段、6・Φ・・領域内配線手段、
T・・・・配線データ。
The figure is a block diagram showing an embodiment of the wiring processing method according to the present invention. 1...-Wiring section data, 2e...Fault data, 3
...Division instruction data, 4...Area division means, 5
... Inter-area wiring means, 6.Φ... Intra-area wiring means,
T...Wiring data.

Claims (1)

【特許請求の範囲】[Claims]  プリント配線板、セラミック配線板などの配線設計に
おける結線すべき2点間の配線処理を基板上に配線処理
用の配線格子を設定して処理する配線処理方式において
、基板を任意の数に領域分割する領域分割手段と、各領
域間にまたがる配線区間の配線を許容配線格子の1/N
(ただしN≧1)の配線格子のみを使用して配線する領
域間配線手段と、各領域内の配線区間の配線を許容配線
格子を使用して各領域単位に配線する領域内配線手段と
を備えたことを特徴とする配線処理方式。
In the wiring processing method that processes the wiring between two points to be connected in the wiring design of printed wiring boards, ceramic wiring boards, etc. by setting a wiring grid for wiring processing on the board, the board is divided into an arbitrary number of areas. area dividing means to allow wiring in the wiring section spanning between each area to 1/N of the wiring grid.
(However, N≧1) Inter-region wiring means for wiring using only the wiring grid, and intra-region wiring means for wiring the wiring section in each region in each region using the permissible wiring grid. A wiring processing method characterized by:
JP61284159A 1986-12-01 1986-12-01 Wiring processing system Pending JPS63138467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61284159A JPS63138467A (en) 1986-12-01 1986-12-01 Wiring processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61284159A JPS63138467A (en) 1986-12-01 1986-12-01 Wiring processing system

Publications (1)

Publication Number Publication Date
JPS63138467A true JPS63138467A (en) 1988-06-10

Family

ID=17674943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61284159A Pending JPS63138467A (en) 1986-12-01 1986-12-01 Wiring processing system

Country Status (1)

Country Link
JP (1) JPS63138467A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04151771A (en) * 1990-10-16 1992-05-25 Nec Corp Wiring system for circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04151771A (en) * 1990-10-16 1992-05-25 Nec Corp Wiring system for circuit board

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