JPS63137332A - Computer - Google Patents

Abstract

PURPOSE:To multiplex instructions and addressing modes by providing an effective address forming adder with an adding/subtracting function based upon an increment, a decrement and a constant and allowing the adder to be accessed as an operand of an instruction. CONSTITUTION:The adder 9 is allowed to add/subtract an increment/decrement and a constant and a signal line connected to a multiplexer 2 connected to the adder 9 is formed as a bidirectional signal line. Since the adder 9 is provided with said function, continuous addresses or addresses arranged very fixed address can be rapidly calculated. Since the bidirectional signal line 10 is formed, an instruction for adding the contents of a register to that of an effective address generator can be also formed and the value of the effective address generator is sent to the bidirectional signal line 10 through a latch 7 and a latch output 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a computer, and particularly to an improvement in the effective address calculation method thereof.

[Conventional technology]

As the addressing mode of computers becomes more complex and the address space increases, instead of specifying the address to be accessed externally each time, it is possible to actually access the address sequentially internally based on a given address. An effective address generator is used to generate the correct address.

The following formula A shows the computer instructions in a general binary form: MOV(Re+IX-kDIs:), Rm
(A) [Contents of register Re, contents of index register IX, and displacement D given as a constant! ``Transfer the contents of the memory whose address is the value obtained by adding the value of ``S'' to the register Rm.'' In this way, a complicated addressing mode is used to determine one address.

Table 1 below outlines an example of a conventional procedure for executing the instruction shown in equation A using a revocation address generator.

Table 1 m In Table 1 (a) above, disabled men)D
The ISO value is loaded into the effective address generator.

In Table (b), the contents of index register tX are loaded into the effective address generator. At 3 in Table (c), the displacement DIS already loaded in the revocation address generator is added to the value of the index register IX.

In table (d), the contents of register Re are first loaded into the effective address generator. In the same table (e), the already added result of IX +DIS and the contents of the loaded register Re are added. In Table (f), data accessed by the effective address calculated by the effective address generator is loaded into register Rm.

FIG. 2 shows an example of an outline of a conventional revocation address generator that performs the operations shown in Table 1.
(1) is an adder, (21 is a multiplexer, (3) is the data input of multiplexer (2), (4) and (6)
is connected to the adder il+ at the data output of the multiplexer (2). The data on data input (3) is multiplexed by multiplexer (2) and the output +41
Alternatively, it is input to the adder (1) from (5). (6)
is the output of the adder 111, (7) is a latch whose input is the adder output (6), and (8) is the output of the latch (7), which is connected to one of the inputs of the adder (1). The circuits of the adder il+ and the multiplexer (2) can be easily realized using generally known circuits. Note that although signals for controlling the effective address generator are not shown in FIG. 2, it is a matter of course that a computer generates control signals according to instructions.

[Problem that the invention seeks to solve]

In order to generate an effective address in the conventional address generator shown in FIG. 2, it is necessary to go through the steps shown in Table 1. Or, if addresses lined up at regular intervals are accessed using the same addressing mode of the same instruction, it is necessary to generate an effective address according to the addressing mode each time the instruction is executed.
It took a lot of time to execute the command.

This invention was made to solve the above problems, and is a computer that can shorten execution time when accessing consecutive addresses or addresses lined up at regular intervals using the same instruction and the same addressing mode. The purpose is to obtain.

[Means for solving problems]

In the computer according to the present invention, an adder constituting an effective address generator is provided with an increment or decrement function, a constant addition or subtraction function, or an operation function with a register, and the effective address generator is used as an operand of an instruction. It can be accessed as .

[Effect]

In the computer according to the present invention, the above-described configuration of the effective address generator and new instructions that use the effective address generator as operands are added, thereby reducing the processing time while leaving the instruction decoding circuit, arithmetic control circuit, etc. as before. It can be shortened.

(9) is an adder that can increment or decrement the operation result, (lO)
is connected to the multiplexer (2) by a bidirectional signal line, and data to be added by the adder (9) is input.

(11) is the output of the latch (7), which is connected to the adder (9) and the signal line (lO), and outputs the output of the latch (7) to the signal line (lO). The other end of the signal line (lO) is connected to a register (not shown) or the like. The signals controlling the effective address generator are not shown in FIG.

Now, a new instruction for incrementing the contents of the effective address generator is defined as INCRAG, and the calculator is made to generate a control signal in accordance with this instruction. This control signal causes the adder (9) to increment the expired address held by the adder itself. Therefore, the time required to calculate the effective address is extremely short.

Furthermore, by equipping a computer with instructions other than simply transferring the contents of the effective address generator to a register or the like, more complex addressing methods can be performed in a shorter execution time.

For example, an instruction to add the contents of a register and the contents of an expiration address generator is defined as ADDR, EAG, and the computer generates a control signal in accordance with this instruction. With this control signal, for example, the value of the effective address generator is output via the latch (7) and the latch output (II) to both data lines (10).

Then, it is sent to, for example, an accumulator (not shown) and is calculated. It is also easy to return the calculated result to the revocation address generator. For this purpose, a path for transferring data from the bidirectional data line (lO) to the adder (9) can also be provided.

Furthermore, in addition to data transfer and yI4 arithmetic, even if it is combined with instructions such as judgment and jump, the speed of the operation can be increased.

〔Effect of the invention〕

As described above, in the computer according to the present invention, the adder constituting the effective address generator has the function of incrementing or decrementing or adding or subtracting a constant, and the effective address generator can be accessed as an operand of an instruction. This makes it possible to diversify instructions and addressing modes, and shorten instruction execution time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an effective address generator according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a revocation address generator of a conventional computer. In the figure, (2) is a multiplexer, (71 is a latch, and (9) is an adder. In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (6)

[Claims] (1) A computer having an effective address generator that calculates an effective address, which has a function of incrementing or decrementing the value of the effective address in the effective address generator, or adding or subtracting a constant from the value, and A computer characterized by having an instruction having an effective address generator as its operand. (2) The first effective address generator includes a first effective address generator for instruction access and a second effective address generator for data access. Calculator described in Section 1. (3) The computer according to claim 1, further comprising a data transfer instruction as the instruction. (4) The computer according to claim 1, further comprising an arithmetic instruction as the instruction. (5) The computer according to claim 1, further comprising a determination instruction as the instruction. (6) The computer according to claim 1, further comprising a jump instruction as the instruction.