JPS631365A - Reference voltage generator circuit - Google Patents

Reference voltage generator circuit

Info

Publication number
JPS631365A
JPS631365A JP14191086A JP14191086A JPS631365A JP S631365 A JPS631365 A JP S631365A JP 14191086 A JP14191086 A JP 14191086A JP 14191086 A JP14191086 A JP 14191086A JP S631365 A JPS631365 A JP S631365A
Authority
JP
Japan
Prior art keywords
voltage
reference voltage
circuit
power supply
smoothing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14191086A
Other languages
Japanese (ja)
Inventor
Michiharu Yomo
四方 道治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14191086A priority Critical patent/JPS631365A/en
Publication of JPS631365A publication Critical patent/JPS631365A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce noises from a power source and other signal line by inserting smoothing condensers between the output voltage of a voltage controller and one power terminal voltage, and between the output voltage of the controller and other power terminal voltage. CONSTITUTION:Smoothing condensers C2, C1 are respectively inserted between the output voltage Vc of a voltage controller and one power terminal voltage Vcc, and between the output voltage Vc and the other power terminal voltage Vss in the voltage smoothing circuit of a reference voltage generator 1. The influence of a power source variation with respect to the output voltage Vc can be completely cancelled by equalizing the capacities of the condensers C1, C2.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、大規模集積化された半導体装置に組み込まれ
た基準電圧発生回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a reference voltage generation circuit incorporated in a large-scale integrated semiconductor device.

従来の技術 近年、半導体装置の大規模集積化が進むにつれ、その機
能も多様化の一途をたどってきた。このような中で、半
導体装置の中に基準電圧発生回路を組み込み、これによ
り発生した基準電圧と外部端子に印加された信号の電圧
を比較するという方法で、各種モードの検出などが行な
われるようになってきており、その際、正確な基準電圧
を発生させることが、半導体装置の高性能化および安定
動作実現のための一要件となってきた。
BACKGROUND OF THE INVENTION In recent years, as semiconductor devices have become more integrated on a large scale, their functions have also become more diverse. Under these circumstances, various modes have been detected by incorporating a reference voltage generation circuit into a semiconductor device and comparing the reference voltage generated by the circuit with the voltage of a signal applied to an external terminal. At this time, generating an accurate reference voltage has become a requirement for realizing high performance and stable operation of semiconductor devices.

以下に、従来の基準電圧発生回路について説明する。第
3図は、従来の基準電圧発生回路の一例について、その
回路図を半導体装置に組み込んだ形で示すものであり、
第4図は、この半導体装置の動作時の波形を模式的に示
すものである。
A conventional reference voltage generation circuit will be explained below. FIG. 3 shows a circuit diagram of an example of a conventional reference voltage generation circuit incorporated in a semiconductor device.
FIG. 4 schematically shows waveforms during operation of this semiconductor device.

第3図で、1で示した破線内の回路が基準電圧発生回路
であり、ここでは、2の半導体装面内に組み込まれてい
る。すなわち、この半導体装置2内には、基準電圧発生
回路の他に、内部回路(基準電圧発生回路以外の全回路
)3および、基準電圧と外部端子電圧を比較するための
比較器6が含まれている。この他、半導体装置2の外側
には半導体装置の電源を供給するための外部電源4、外
部端子電圧供給源5が示されている。第3図において、
基準電圧発生回路1は、2つの電圧制御用抵抗RI.R
2および平滑用コンデンサC1で構成されており、基準
電圧発生回路の出力電圧VCは、で与えられる電圧とな
る。ここで、Rl,R2は、待機時電源電流を抑えるな
どの目的のために十分に高い抵抗値(数十キロオーム以
上)に設定するのが一般である。このため半導体装置内
の他の信号との間の容量カップリング等による雑音を受
けやすくなり、これを平滑化するために、基準電圧出力
と電源の間に平滑コンデンサC!を挿入することになる
。(C+ は、基準電圧発生回路出力ノードと信号線の
間の浮遊容量に比べて十分大きな値。)以上の説明では
、基準電圧発生回路の電圧制御回路として抵抗R..R
2による抵抗分割方式を例示したが、抵抗の代わりにト
ランジスタ(例えば、ゲート・ソースをショートしたデ
プレーション型MOS}ランジスタ)を用いてもよいし
、抵抗とトランジスタを並列に接続した形を用いてもよ
い。
In FIG. 3, the circuit within the broken line indicated by 1 is the reference voltage generating circuit, which is incorporated within the semiconductor device 2 here. That is, in addition to the reference voltage generation circuit, this semiconductor device 2 includes an internal circuit (all circuits other than the reference voltage generation circuit) 3 and a comparator 6 for comparing the reference voltage and the external terminal voltage. ing. In addition, an external power source 4 and an external terminal voltage supply source 5 for supplying power to the semiconductor device are shown on the outside of the semiconductor device 2. In Figure 3,
The reference voltage generation circuit 1 includes two voltage control resistors RI. R
2 and a smoothing capacitor C1, and the output voltage VC of the reference voltage generating circuit is a voltage given by. Here, Rl and R2 are generally set to sufficiently high resistance values (several tens of kilohms or more) for purposes such as suppressing standby power supply current. This makes it susceptible to noise due to capacitive coupling with other signals within the semiconductor device, and in order to smooth this out, a smoothing capacitor C! is placed between the reference voltage output and the power supply. will be inserted. (C+ is a value that is sufficiently large compared to the stray capacitance between the reference voltage generation circuit output node and the signal line.) In the above explanation, the resistor R. .. R
Although the resistor division method according to No. 2 has been exemplified, a transistor (for example, a depletion type MOS transistor with the gate and source shorted) may be used instead of the resistor, or a resistor and a transistor connected in parallel may be used. Good too.

発明が解決しようとする問題点 上記のような従来の方式では、基準電圧発生回路の出力
電圧Vcが、電源電圧の変動の影響を直接被ることにな
る。すなわち、第3図に示すように、外部電源4のプラ
ス側端子V CC−EX丁と基準電圧発生回路が組み込
まれた半導体装置の電源端子VCCの間には、半導体装
置外部の電源配線の抵抗,パッケージングの配線抵抗,
ボンディングワイヤー,半導体装置内配線抵抗などによ
り構成される等価抵抗10が存在する。また、実際には
配線インダクタンスの影響も無視できず、むしろ、抵抗
よりも重要と考えられる。同様にV SS−EX丁とV
SSの間にも等価抵抗Rl1が存在する。さらに、半導
体装置の動作時においては、内部回路3に電流が流れる
ため、VCC側の等価抵抗Rho. Vss{tlII
の等価抵抗Rl1に第3図に示したI3なる電流が流れ
る。
Problems to be Solved by the Invention In the conventional system as described above, the output voltage Vc of the reference voltage generation circuit is directly affected by fluctuations in the power supply voltage. That is, as shown in FIG. 3, between the positive terminal VCC-EX of the external power supply 4 and the power supply terminal VCC of the semiconductor device in which the reference voltage generation circuit is incorporated, there is a resistance of the power supply wiring external to the semiconductor device. , packaging wiring resistance,
There is an equivalent resistance 10 composed of bonding wires, wiring resistance within the semiconductor device, and the like. Furthermore, in reality, the influence of wiring inductance cannot be ignored, and is considered to be more important than resistance. Similarly, V SS-EX and V
An equivalent resistance Rl1 also exists between SS. Furthermore, since a current flows through the internal circuit 3 during operation of the semiconductor device, the equivalent resistance Rho on the VCC side. Vss{tlII
A current I3 shown in FIG. 3 flows through the equivalent resistance Rl1.

この電流波形の模式図は第4図に示した。なお、基準電
圧発生回路を流れる電流は、R,.R2が十分高抵抗で
あるので無視した。その結果、半導体装置の電源ノード
VCC.VSSは、各等価抵抗RIG.R目の電圧降下
により、第4図に示したような波形となる。ここで、基
準電圧発生回路のCIとR1またはCI とR2によっ
て決まる時定数に比べて半導体装置の動作周期が十分短
かい場合、第4図に示すように,基準電圧Vcは、C1
を介してのVSSとの容量カップリングにより雑音を受
けることになる。そして第3図のVEXTのようなV 
SS−EXTを基準とした外部電圧のハイ,ローを判定
する比較電圧として、このvcを用いた場合、誤判定を
引きおこすことになる。
A schematic diagram of this current waveform is shown in FIG. Note that the current flowing through the reference voltage generation circuit is R, . Since R2 has a sufficiently high resistance, it was ignored. As a result, the power supply node VCC of the semiconductor device. VSS is equal to each equivalent resistance RIG. Due to the voltage drop at the Rth point, a waveform as shown in FIG. 4 is obtained. Here, if the operating cycle of the semiconductor device is sufficiently short compared to the time constant determined by CI and R1 or CI and R2 of the reference voltage generation circuit, the reference voltage Vc is
It will be subject to noise due to capacitive coupling with VSS via. And a V like VEXT in Figure 3
If this vc is used as a comparison voltage for determining whether the external voltage is high or low based on SS-EXT, an erroneous determination will occur.

このように、従来の基準電圧発生回路では、信号線から
の雑音低減のための平滑コンデンサを介して電源変動の
影響を直接受けてしまうため、結果的には、雑音低減に
ほど遠いものとなってしまうという問題点があった。
In this way, conventional reference voltage generation circuits are directly affected by power supply fluctuations through the smoothing capacitor used to reduce noise from the signal line, and as a result, they are far from being able to reduce noise. There was a problem with it being put away.

本発明は、上記従来の問題点を解消するもので、電源お
よび他の信号線からの雑音を同時に大きく低減できる平
滑回路を備えた基準電圧発生回路を提供することを目的
とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a reference voltage generation circuit equipped with a smoothing circuit that can simultaneously greatly reduce noise from a power supply and other signal lines.

問題点を解決するための手段 本発明は、一定電位の第1の電源と、一定電位の第2の
電源と、前記第1,第2の電源の中間の任意の電位を発
生・出力する電圧制御回路と、前記電圧制御回路の出力
電圧を平滑化する電圧平滑回路とを具え、前記電圧平滑
回路が、両端が前記電圧制御回路の出力と前記第1の電
源に接続されたコンデンサと、両端が前記電圧制御回路
の出力と前記第2の電源に接続されたコンデンサにより
構成された基準電圧発生回路である。
Means for Solving the Problems The present invention provides a first power source with a constant potential, a second power source with a constant potential, and a voltage that generates and outputs an arbitrary potential between the first and second power sources. a control circuit; and a voltage smoothing circuit for smoothing the output voltage of the voltage control circuit, the voltage smoothing circuit having a capacitor connected at both ends to the output of the voltage control circuit and the first power source; is a reference voltage generation circuit constituted by the output of the voltage control circuit and a capacitor connected to the second power supply.

作用 本発明によれば、半導体装置に組み込まれた基準電圧発
生回路における電源および他の信号線からの雑音を同時
に、しかも無視できるレベルまで低減することが可能に
なり、安定な基準電圧発生回路を提供するところとなる
Effect of the Invention According to the present invention, it is possible to simultaneously reduce noise from the power supply and other signal lines in a reference voltage generation circuit incorporated in a semiconductor device to a negligible level, thereby creating a stable reference voltage generation circuit. It will be provided.

実施例 第1図は、本発明の実施例における基準電圧発生回路を
半導体装置に組み込んだ形で示すものであり、第2図は
、第1図の回路における主要ノードの動作波形を模式的
に示している。
Embodiment FIG. 1 shows a reference voltage generation circuit according to an embodiment of the present invention incorporated into a semiconductor device, and FIG. 2 schematically shows operating waveforms of main nodes in the circuit of FIG. It shows.

第3図に示した従来の基準電圧発生回路において、電圧
平滑回路部分が電圧制御回路の出力VcとVSSの間に
挿入されたコンデンサC1のみから構成されていたのに
比して、第1図示の基準電圧発生回路では、電圧平滑回
路部分が電圧制御回路路の出力VCとVSSの間のコン
デンサC1とVcとVCCの間のコンデンサC2から構
成されている。
In the conventional reference voltage generation circuit shown in FIG. 3, the voltage smoothing circuit part was composed only of the capacitor C1 inserted between the output Vc and VSS of the voltage control circuit. In the reference voltage generating circuit shown in FIG. 1, the voltage smoothing circuit portion is composed of a capacitor C1 between the outputs VC and VSS of the voltage control circuit, and a capacitor C2 between Vc and VCC.

第1図における等価抵抗RIGとRl1の値が等しい場
合を考えると、半導体装置1を流れる電流I3(第2図
柄照)による等価抵抗RIG. Rllの電圧降下01
, 7J2 (第2図参照)は等しい値となるため明ら
かに、コンデンサCIと02を等しい容量とすることで
、VCに対する電源変動の影響は完全に相殺することが
できる。また、各等価抵抗RIO.Rl+の抵抗値が異
なる場合でも、 CI/C2=RIO/RII= l U+ l/l02
l−=■の関係に従ってcl,c2の容量値を決定すれ
ば同様の効果が得られる。また、このとき、Vcと半導
体装置内の他の信号線との間の浮遊容量に比してC.,
c2を十分大きな値にしておけば、Vcに対する他の信
号線からの容量カップル雑音も無視できる大きさとする
ことができる。
Considering the case where the equivalent resistances RIG and Rl1 in FIG. 1 have the same value, the equivalent resistance RIG. Rll voltage drop 01
, 7J2 (see FIG. 2) have the same value, so it is clear that by setting the capacitors CI and 02 to have the same capacity, the influence of power supply fluctuations on VC can be completely canceled out. In addition, each equivalent resistance RIO. Even if the resistance value of Rl+ is different, CI/C2=RIO/RII= l U+ l/l02
A similar effect can be obtained by determining the capacitance values of cl and c2 according to the relationship l-=■. Also, at this time, C. ,
If c2 is set to a sufficiently large value, capacitive couple noise from other signal lines to Vc can also be made negligible.

以上のように、本実施例によれば、コンデンサC1と0
2の値を適当な値に設定することで、基準電圧VCに対
する電源変動の影響をキャンセルでき、同時に他の信号
線からの雑音も大きく低減できる。なお、実際には、等
価抵抗RIO, Rl+の構成要素のほかに、インダク
タンス成分等も当然含まれ、線路インピーダンスは、等
価抵抗RIO. Rl+のような単純化した形で表現で
きない場合も数多い。このような場合には、例えば第2
図の7JI, 02の値を実測する等の方法で前述の(
2)式を用いてCI.C2の容量値を決定すればよい。
As described above, according to this embodiment, capacitor C1 and 0
By setting the value of 2 to an appropriate value, the influence of power supply fluctuations on the reference voltage VC can be canceled, and at the same time, noise from other signal lines can be greatly reduced. In reality, in addition to the components of the equivalent resistances RIO and Rl+, inductance components are naturally included, and the line impedance is equal to the equivalent resistance RIO. There are many cases that cannot be expressed in a simplified form such as Rl+. In such a case, for example, the second
By actually measuring the values of 7JI and 02 in the figure,
2) CI. What is necessary is to determine the capacitance value of C2.

発明の効果 本発明の基準電圧発生回路は、電圧平滑回路部分におい
て、電圧制御回路の出力電圧VCと一方の電源端子電圧
VCCとの間、そして、VCと他方の電源端子電圧Vc
cとの間にそれぞれ平滑コンデンサを挿入することで、
電源ラインの電圧降下による電源変動が出力電圧vcに
およぼす影響を相殺したものであり、これにより半導体
装置に組み込んだ場合にも、なお安定で雑音の小さな基
準電圧発生が容易に実現され、高性能な準電圧発生回路
を得ることができ、その実用的効果は大きい。
Effects of the Invention The reference voltage generation circuit of the present invention has a voltage smoothing circuit portion that is connected between the output voltage VC of the voltage control circuit and one power supply terminal voltage VCC, and between VC and the other power supply terminal voltage Vc.
By inserting a smoothing capacitor between each c,
This cancels out the effect of power supply fluctuations due to voltage drops in the power supply line on the output voltage VC, and as a result, even when incorporated into a semiconductor device, stable and low-noise reference voltage generation can be easily achieved, resulting in high performance. It is possible to obtain a quasi-voltage generating circuit which has a great practical effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例における基準電圧発生回路の回
路図、第2図は本発明の実施例における基準電圧発生回
路の第1図各ノードにおける波形の模式図、第3図は従
来の方式による基準電圧発生回路側の回路図、第4図は
基準電圧発生回路の従来例第3図の各ノードにおける波
形の模式図である。 VCC−EXT+ VSS−EXT. Vl!XT. 
vcc, vss ”””電源ノード、Rl, R2,
 RIO, R目・・・・・・抵抗、C+・C2・・・
・・・コンデンサ、II.  I2.  13・・・・
・・電流値、U,,02・・・・・・電圧値、Vc・・
・・・・回路出力ノード。 代理人の氏名 弁理士 中尾敏男 ほか1名第1図 第 2 図 −P−亥リ 4一  隼8P電源、 s−3ワLJ『鮭あ5シ・昌ク:コ三ブノ(:拾シ厚6
−pドふ
FIG. 1 is a circuit diagram of a reference voltage generation circuit according to an embodiment of the present invention, FIG. 2 is a schematic diagram of waveforms at each node in FIG. 1 of the reference voltage generation circuit according to an embodiment of the present invention, and FIG. FIG. 4 is a schematic diagram of waveforms at each node of the conventional example of the reference voltage generation circuit shown in FIG. 3. VCC-EXT+ VSS-EXT. Vl! XT.
vcc, vss """ power supply node, Rl, R2,
RIO, Rth...Resistance, C+/C2...
... Capacitor, II. I2. 13...
...Current value, U,,02...Voltage value, Vc...
...Circuit output node. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 6
-p dofu

Claims (1)

【特許請求の範囲】[Claims] 一定電位の第1の電源と、一定電位の第2の電源と、前
記第1、第2の電源の中間の任意の電位を発生・出力す
る電圧制御回路と、前記電圧制御回路の出力電圧を平滑
化する電圧平滑回路とを具え、前記電圧平滑回路が、両
端が前記電圧制御回路の出力と前記第1の電源に接続さ
れたコンデンサと、両端が前記電圧制御回路の出力と前
記第2の電源に接続されたコンデンサにより構成される
ことを特徴とする基準電圧発生回路。
A first power supply with a constant potential, a second power supply with a constant potential, a voltage control circuit that generates and outputs an arbitrary potential between the first and second power supplies, and an output voltage of the voltage control circuit. a voltage smoothing circuit for smoothing, the voltage smoothing circuit having both ends connected to the output of the voltage control circuit and the first power supply, and having both ends connected to the output of the voltage control circuit and the second power supply. A reference voltage generation circuit comprising a capacitor connected to a power supply.
JP14191086A 1986-06-18 1986-06-18 Reference voltage generator circuit Pending JPS631365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14191086A JPS631365A (en) 1986-06-18 1986-06-18 Reference voltage generator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14191086A JPS631365A (en) 1986-06-18 1986-06-18 Reference voltage generator circuit

Publications (1)

Publication Number Publication Date
JPS631365A true JPS631365A (en) 1988-01-06

Family

ID=15303004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14191086A Pending JPS631365A (en) 1986-06-18 1986-06-18 Reference voltage generator circuit

Country Status (1)

Country Link
JP (1) JPS631365A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009168644A (en) * 2008-01-17 2009-07-30 Tdk Corp Magnetic balance type current sensor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113602A (en) * 1980-12-29 1982-07-15 Nec Corp Integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113602A (en) * 1980-12-29 1982-07-15 Nec Corp Integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009168644A (en) * 2008-01-17 2009-07-30 Tdk Corp Magnetic balance type current sensor

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