JPS63134569U - - Google Patents
Info
- Publication number
- JPS63134569U JPS63134569U JP2650887U JP2650887U JPS63134569U JP S63134569 U JPS63134569 U JP S63134569U JP 2650887 U JP2650887 U JP 2650887U JP 2650887 U JP2650887 U JP 2650887U JP S63134569 U JPS63134569 U JP S63134569U
- Authority
- JP
- Japan
- Prior art keywords
- hole
- wiring board
- printed wiring
- filled
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000007747 plating Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2650887U JPS63134569U (en:Method) | 1987-02-24 | 1987-02-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2650887U JPS63134569U (en:Method) | 1987-02-24 | 1987-02-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63134569U true JPS63134569U (en:Method) | 1988-09-02 |
Family
ID=30827655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2650887U Pending JPS63134569U (en:Method) | 1987-02-24 | 1987-02-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63134569U (en:Method) |
-
1987
- 1987-02-24 JP JP2650887U patent/JPS63134569U/ja active Pending