JPS6313216B2 - - Google Patents

Description

Claim 1: A data processing system for executing an instruction code comprising a main memory and comprising an operator and an object code including a main memory address, the data processing system comprising: a main memory; means for determining when to indicate a logical non-dependence that does not require the processing result of a logically non-dependent operator and placing a string consisting of said logically non-dependent operator and a subsequent logically dependent operator in a logically non-dependent queue; means for storing said formed logically independent queues; a plurality of processing means connected to said storing means and each receiving a separate one of said queues for simultaneous execution; each of the means includes a local memory, main memory address means for receiving a main memory address included in said instruction code and retrieving data from a corresponding main memory storage location; local memory addressing means for providing a local memory address to said main memory corresponding to a string, thereby enabling data retrieved from said main memory to be transferred to a corresponding storage location in said local memory. , data processing systems. 2. Data processing according to claim 1, wherein said local memory address means are adapted to append said local memory address to a corresponding string of operators constituting a particular logically independent queue. system. 3. A data processing method in a data processing system for receiving and executing a sequential code of object code including a main memory and having an operator and a main memory address, the processing system comprising a plurality of main memory devices each having a local memory. processing means, receiving said sequential object code, determining when an operator exhibits a logical non-dependency that does not require the result of a previous processing, and processing means for processing logically non-dependent operators and subsequent logical make strings of operators subordinate to logically independent queues, retrieve data from corresponding storage locations in said main memory in response to a main memory address contained in an object code, and write each string in said queue to a logically independent queue; correspondingly providing a local memory address to said main memory, thereby transferring retrieved data from said main memory to a corresponding local memory storage location, and distributing separate ones of said queues for simultaneous execution; A data processing method that involves transferring data to different individual processing means. 4. The data processing method of claim 3, further comprising appending the local memory address to a corresponding string of operators configuring a particular logically independent queue. 5. said data processing system includes a job queue, said logically independent queue of operators and corresponding local memory addresses to said job queue for subsequent distribution to different ones of said processing means; 5. The data processing method according to claim 4, further comprising transferring. Specification The following U.S. patent applications are directly or indirectly related to this application: Application No. 386339 entitled "Mechanism for Generating Dependent Free Codes for Multiprocessing Elements" filed by Alfred J. De Santis et al. on June 8, 1982 (Japanese Patent Application No. 59-501133) ). Application No. 386420 entitled "System and Method for Renaming Data Items for Dependent Free Codes" filed by Alfred J. De Santis on June 8, 1982
No. 501132). BACKGROUND OF THE INVENTION Field of the Invention This invention relates to mechanisms for generating dependent free code, and more particularly to such mechanisms for using multiple simultaneous processing elements. Description of the Prior Art Even today, most computers are of the Von Neuman type, driven by and executing instruction languages that are sequential in nature. Furthermore, such sequential languages contain many dependencies between individual instructions, such that individual instructions cannot be executed out of order. For example, consider the following sequence. C:=Fn(A,B) D:=Fn+i(C,E) These two functions Fn and Fn+i have logical dependence because the result of the function Fn is used as the input to the next function Fn+i. are doing. Additionally, a drawback of sequential languages is that there is redundancy in memory fetching and code processing when a sequence or loop is repeated;
If it were improved, the processor throughput would be increased. One way to increase the throughput of a processing system is to use multiple processors in multiprocessing mode. However, the individual processors must still execute instructions sequentially, and the only simultaneous processing occurs when the individual processors are executing separate segments of the program, or when they are executing completely different programs. It exists only when it exists. Such multiprocessing systems are described, for example, in U.S. Pat. No. 3,319,226 to Mott et al.
As disclosed in Anderson et al., US Pat. No. 3,419,849. Yet another attempt to increase throughput is to employ pipelining, in which the various subfunctions of instruction execution overlap. By overlapping these steps with a series of instructions, instruction execution can occur every clock time, thereby increasing processor throughput. All these methods for increasing throughput are designed for sequential instruction execution due to the logical dependencies between instructions as described above.
Because of the logical dependencies, true simultaneous processing cannot be achieved, in which the various instructions are executed independently of each other to easily accommodate processing by a group or multiple processing elements. An application language is an application language in that each statement is essentially independent of each other and can therefore be simultaneously implemented by a network of processing elements designed to reduce such application statements. It is different from command language. An example of such an applied language processor is
U.S. Patent Application No. 281,064 to Bolton et al.
Given in U.S. Patent Application No. 281,065 to Hagenmaier et al. Both of these applications were filed in July 1981.
The application was filed on May 7th and assigned to the assignee of the present application.
Such application languages are
It differs from command languages in that it is not sequential in the Von Neuman sense. However, most program libraries used today are written in imperative languages, and updates or even further generations of data processing systems that use those libraries must be made to implement imperative languages. One way in which processing power can be increased is by recognizing segments of object code that are independent of the results of previous processing and placing those segments into non-dependent sequences or queues that can be processed simultaneously by multiple processing elements. It is to form.
This, of course, requires handling of the operand in such a way that operations can be performed on the operand without destroying its original value as it resides in memory. Different symbolic names may be specified to refer to any data item for this purpose. The arrangement of such a queue of codes or symbols further accommodates simultaneous processing by the processing unit. It is an object of this invention to provide an improved mechanism for generating dependent free instruction codes. Another object of the invention is to provide dependent-free instruction code for execution by multiple processing elements. Yet another object of the invention is to provide an improved mechanism for providing dependent free instruction codes to multiple processing elements in a simultaneous manner. Yet another object of the invention is to provide a mechanism for generating instruction codes which are characterized by the fact that there are no redundant memory fetches and that the code does not have to be reprocessed for the processing of a series of such codes. It is to provide. Summary of the invention In order to achieve the above-mentioned object, this invention
taking a string of object code and forming them into higher-level tasks and determining sequences of such tasks that are logically non-dependent so that they are executed separately;
It is directed to a cache mechanism for data processors. This cache mechanism performs all memory accesses required by the various tasks and stores these tasks with corresponding pointers or references to local memory where the various data items have not been stored. This cache mechanism utilizes a symbol translation table in which tasks are stored in a queue with symbols representing various references or pointers to local memory. In this way, different data items can be assigned different symbols or symbolic names for use in different tasks, thus limiting dependencies between different tasks and controlling data modification. A feature of the invention is to provide a cache mechanism for a group of processing elements that forms a string of sequential object codes into queues of tasks, each queue being logically distinct from the others. It is essentially non-dependent.

[Brief explanation of the drawing]

The above objects and other objects, effects, and features of the present invention will become more apparent from the following detailed description with reference to the drawings. FIG. 1 is a string of object codes and the corresponding logically independent queues formed from the object codes for which the present invention is designed. FIG. 2 is a schematic block diagram of a system according to the invention. FIG. 3 shows the format of a queue created in accordance with the present invention. FIG. 4 is a schematic block diagram of a symbol translation table module used in the present invention. FIG. 5 is a schematic block diagram of processing elements used in the present invention. FIG. 6 is a timing diagram illustrating the invention. SUMMARY DESCRIPTION OF THE INVENTION To achieve the above objects, advantages and features, the present invention utilizes three different aspects: improved code processing with multiple processing elements;
Has reference processing and parallel execution. In code processing, the invention first preprocesses an instruction string by concatenation, examines the relationship between a series of concatenated instructions, and concatenates the instructions together to form a queue of dependent instructions. The mechanism used to determine whether concatenated instructions should be concatenated together is dependence on one concatenated instruction that provides output for subsequent concatenated instructions. Once a non-dependency is located, a queue is formed. Once a queue is formed, the mechanism according to the invention is effective by processing the entire queue in one step. What would normally require several cycles to reprocess concatenated instructions is now done in one cycle, and the queue does not need to be regenerated for the execution of a sequence. Furthermore, during processing of the code, operand references that have been previously referenced and are local to the processing element can be recognized. This is accomplished by receiving each reference and scanning the translation table to see if the item is in the processor's local memory. If a reference does not reside in the processor's local memory, the invention assigns a symbol to the reference, and the individual symbol corresponding to any queue is appended thereto for subsequent transfer to a processing element. Once corresponding queues are created, they can be executed simultaneously by multiple processing elements. In the design of today's processing systems, there is a tendency to use stack-oriented processors, where push-down stacks, or first-in, last-out stacks are given, and the recursion used by certain high-level programming languages is used. Adapt procedures and nested processing. Given such a stack-oriented processor, the parent control program and other routines that form part of the processing system can be written in certain high-level languages that are recursive in nature, such as Algol. can. A particular processor of this form is
As disclosed in Barton et al. patents 3461423, 3546677, and 3548384. The function of the stack mechanism, a first-in, last-out mechanism, is to manipulate instructions and associated parameters in a manner that reflects the nested structure of a particular high-level language. Such a stack resides conceptually in main memory, and the processor's stack mechanism is adapted to contain a reference to the top data item in the stack. In this way, many different stacks of data items reside in memory, and the processor accesses them according to their addresses to the tops of stack registers present in the processor, with the various stacks containing the contents of those registers. Can be accessed at different times depending on the change. If the processor is not provided with such a stacking mechanism, it implements a recursive type of language by addressing its general purpose registers even though they are a hardware stacking mechanism. Although the preferred embodiment of this invention is directed to such a stack-oriented processor for executing programs written in high-level recursive languages, the subject matter of this invention is to Other types of processors designed to execute types of language programs may also be used. Once a program is written in this high-level language, it is compiled by the processor's compiler into a string of object code or machine language code, the format of which is designed and controlled according to the design of the particular processor.
As mentioned above, most processors designed today are still of the Von Neuman type;
It is sequential in nature and contains many logical dependencies. To generally demonstrate how the invention provides dependent-free code in the form of "decompiled" high-level language code, the first
See diagram. The left column of Figure 1 shows C[I, J]:=
Represents a string of machine language code for the calculation of A[I,J]+B[I,J]. Since this calculation is for many addresses, the string of machine language code shown at the far left of FIG. 1 is executed in a sequence or series of loops. This string of codes is divided into four groups or subsets of codes, each group being largely logically independent of the others as shown by the block diagram in the center portion of FIG. . In general, the mechanism of the present invention determines the ends of a logically independent string when the next process is independent of the previous process or stored process. In this invention, the mechanism performs value calls or memory fetches and creates operator queues or data items (or local addresses for data items), as shown in the right column of FIG. These operators and their data items may be concatenated with each other and transferred to processing elements in the manner described below. Such concatenated instructions are hereinafter referred to as tasks. In the example of FIG. 1, the four separate queues are logically non-dependent groups of dependent concatenated instructions that can be executed simultaneously by separate processing elements as described below. Since the string of code in the left column of FIG. 1 should be executed in a sequence of loops, the newly generated queue in the right column of FIG. 1 does not need to be regenerated. All that is required for each series of loops is that new values and array items are retrieved from memory. Also, a new pointer value must be assigned to the variable being stored.

[Detailed description of the invention]

A processor system according to the invention is shown in FIG. 2, in which a cache mechanism 10 provides data references for individual queues of operators and a plurality of small processing elements 11a, b and c, as well as a queue processing element 13a. each of which is provided with its own local memories 12a, b and c and local memory 13b, respectively.
The cache mechanism 10 communicates directly with main memory (not shown), and the individual processing elements also communicate with the main memory by direct storage modules 14. The mechanism 10 consists of four units: a queue task module 10a, an instruction reference module 10b,
It includes a symbol translation module 10c and a job queue 10d. The functions of these individual units will now be briefly explained. The individual strings of object code or machine language code are received from memory by the standby task module 10a, which has a buffer that serially receives each instruction and assembles them into a queue of tasks. or cache memory, where the length of a task's queue depends on logical dependencies between a series of linked characters. Waiting task module 10a includes sufficient decoding circuitry to determine when a concatenated group of instructions does not require the results of a previous computation. Once such a queue of linked tasks has been assembled, its operand references are transferred to the instruction reference module 10b, which is requested by the individual instructions and assignment symbols. Perform arbitrary memory fetches. The waiting task module 10a also assigns a queue number to the symbol translation module 10c. The instruction reference module 10b is an associative memory that determines whether an absolute memory address is logically held; if not, the instruction reference module 10b sends the address to main memory and stores the address. The memory is accessed by assigning a symbol to it. This associative memory then transfers the symbol along with the corresponding task to the symbol translation module 10c. The symbol translation module 10c allocates a pointer (local memory address) to the symbol and transfers the pointer to main memory so that main memory can store the data item therein. During the first execution of the string of object code,
A queue for a series of instructions is formed in the symbol translation module 10c. While these queues are formed, individual tasks and pointers are transferred to job queue 10d. The symbol translation module 10c is a table top up memory having various queue storage locations that can be referenced by the waiting task module 10a. These storage locations contain a list of linked instructions and item symbols maintained in the local memory of the processing element. When each queue is read, the symbol for the queue is used as a read address into a lookup table containing a pointer to the actual storage location of the item referenced by the symbol, as described in more detail below. . At the end of the first processing of the object code string of FIG. It can be fed serially to elements 11a, 11b, and 11c. Meanwhile, individual data items required for execution are retrieved from main memory and stored at appropriate locations in local memories 12a, 12b and 12c, which locations are indicated by pointers in job queue 10d. Accessed once. Completion of the first loop or execution of the object code causes the sequence of operations by feeding previously created queues from symbol translation module 10c to job queue 10d until all task processing has been completed. A loop may be executed. The format in which a queue resides in job queue 10d of FIG. 2 is shown in FIG. Each field read from left to right is a multiply instruction, an add instruction, a subtract instruction, and an index instruction followed by pointers to the I, J, and C fields. These correspond to the first queue (Q ₀ ) in FIG. 1, where an 8-bit literal becomes part of each multiply and add instruction. The queue thus formed not only holds the instruction for future execution, but also identifies the stack environment and its address and storage location of the next queue to be executed. No other processing steps are required for code processing other than providing a queue of available processing elements, one per step. The symbol translation module 10c of FIG. 2 is shown in more detail in FIG. As shown in FIG. 4, this module is a table lookup mechanism, and the columns of the queue symbol table 16 are storage locations for chained tasks as well as symbols assigned by the instruction reference module 10b of FIG. 2, and the corresponding row represents each queue number assigned by the waiting task module 10a of FIG. As mentioned above,
The queue thus formed in the symbolic translation module is similar to the job queue 10d of FIG.
The pointer in pointer table 17 is ready for access for transfer to. Note in FIG. 4 that the various symbols are indirect local memory references, so the items stored therein can be given different pointers. This means that 2
brings two advantages. First, any data item may be stored in one or more locations in local memory by renaming or assigning different pointers to represent it. A second advantage is that any variable can be stored in one storage location and leave it without changing its pointer, while the result of any operation performed on that variable has the same symbolic name. However, it can be stored in another storage location with a different pointer. The individual processing elements of FIG. 2 are illustrated in FIG. In summary, they are formed from multiple microprogrammed microprocessors, and the microprocessors are
8086, or they may be customized microprogrammed processors as disclosed in Faber et al. US Pat. No. 3,983,539. Since the individual processors are adapted to perform different functions, they may be special purpose microprocessors containing only as much logic circuitry as is needed to perform each function. Each circuit 18 includes an arithmetic logic unit, a shift unit, a multiplication unit,
These are an indexing unit, a string processor, and a decoding unit. Additionally, sequencing unit 19 receives instructions from job queue 10d of FIG. 2 and accesses microinstructions stored in control store 20. Microinstructions from the control store are provided to each unit via instruction bus IB, and any status signals generated by the units are transferred via status bus CB. The data from the corresponding local memory is received on the A bus AB, and the executed result is on the B bus.
Supplied to bus BB. Returning to FIG. 1, a more detailed description of the various instructions in the code string being received by the wait task module 10a of FIG. 2 and the higher level instructions or tasks formed by that module. will be performed here. As shown in the left column of Figure 1, the first 3
The three instructions are a value recall or memory fetch of data item I, an 8-bit value, and a multiply instruction. They input the literal value indicated by the next task, the first task in the right column of FIG.
The task of multiplying by, is connected to. The processing is
Continued for addition and subtraction tasks.
A name call instruction is an instruction that places a data item address at the top of the stack, and an index instruction results in the insertion of a pointer in a descriptor located in memory. In this way,
A first queue Q ₀ is formed. The array of Q ₁ is the instruction NXLV after the name call instruction.
is executed to result in index processing and data retrieval. In this way, a second queue O ₁ is formed.
In the array of the third queue _Q2 , there is an add instruction which causes A and B to be stored in this way before the storage of memory (STOD) which destroys the value at the top of the stack. The calculated values are added. As can be seen from the block diagram in the center of Figure 1,
Execution of the last two tasks or chained instructions of Q ₂ requires the results of calculations Q ₀ and Q ₁ whose values are stored in local memory. Its storage location and their respective local memory are given an index flag to indicate whether the reference is actually stored there. In this way, when the processing elements are processed in a concurrent manner, the routine in Q ₂ can reach the second or final addition task before the required values have been calculated and stored in local memory. It is possible. The corresponding processing elements detect that their values are not yet available and continue to access their storage locations until the values become available. The fourth queue, or _Q3 , takes the value J, adds 1 to it, and inserts its address at the top of the stack before performing a non-destructive store in memory, leaving the value at the top of the stack. The last four instructions retrieve the value K from memory, compare it with the value J (LSEQ), and if the value K is greater than the value J, a branch to the next instruction, i.e. false, sets the program counter to It will be reloaded and the routine will repeat. On the other hand, the last instruction in the code string is an unconditional branch that causes the routine to terminate. FIG. 6 is a timing diagram of queue execution times for individual queues, with each clock time for a particular task represented by two numbers. The first number represents the particular loop or sequence that is being executed, and the second number represents the particular processing element that is executing the instructions.
The initial transmission of the code string resulting in the queue arrangement and execution of the task requires approximately 17 clock hours, while the series of loops requires only 5 clock hours to execute. This is because the tasks do not have to be completely reprocessed in QTM and IRM, and the individual dependent free queues are executed concurrently. In general, the wait task module executes concurrent steps of instructions for tasks, waiting for these tasks, queuing execution, tag prediction, and branch correction. The command reference module performs renaming, symbol management, and replacement functions. The symbol translation module provides parallel access, pointer allocation and task allocation. Small processing elements are provided for frequent task execution while unique processing elements are used for infrequent task execution and the functional portion of the string. The direct reference module 15 of FIG. 2 is provided for evaluating non-stack reference. Finally, it takes the compiled object code and forms that sequence of code into a higher-level task, and is not a queue of other queues in the sense that it does not require the results of previous executions of the object code string. A mechanism has been described for a data processor to form a queue of tasks that are logically unrelated. In this manner, sequences of such queues may be provided to non-dependent processing elements for concurrent execution. A symbol translation table is provided by which a data item is referenced, the symbol is assigned an arbitrary pointer to local memory, and the pointer is changed such that the data item is transferred to one or more memory storage locations. The data item may reside in memory, and the data item may remain in memory while the results of operations on that item may be stored in other storage locations. Although one embodiment of the invention has been described, it will be apparent to those skilled in the art that changes and modifications can be made without departing from the spirit of the invention as claimed.