JPS59501131A - Concurrent processing elements for using dependent free codes - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The following U.S. patent applications are directly or indirectly related to this application:

Filed on June 8, 1982 by Δ1fred J, De5antiS, etc. ``Mechanism for Generating Dependent Free Code for Multiprocessing Elements'' Title Application No. 386,339.

By A1fred J, [)e5antis on June 8, 1982 “System for Renaming Data Items for Dependent Free Codes” has been filed. Application No. 386.420 titled ``Systems and Methods''.

The present invention relates to a mechanism for generating dependent free code, and more specifically to a mechanism for generating dependent free code. The present invention relates to such a mechanism for using a number of simultaneous processing elements.

Description of prior art Even today, most computers are built using instruction languages that are sequential in nature. V On N euman type driven or executing such command language belongs to. Moreover, such sequential languages have many subordinations between individual instructions. You cannot belong to it. For example, consider the following sequence.

C:=Fn (A, B> DH=Fn4-i (C,E) These two functions Fn and Fn+i are Arguably, the disadvantage of sequential languages is that they are used as input for sequences or or a loop exists, and if it is improved, the pro Processor throughput will be increased.

One way to increase the processing power of a processing system is to use multiple processors for multiprocessing. It is used in mode. However, individual processors still execute instructions in order. The only concurrent processing is the When running separate segments of RAM or running completely different programs Exist only when you do.

Such a multiprocessing system is described, for example, by Mott et al. No. 3, 319, 226 O and Anderson et al. U.S. Pat. No. 3,41 No. 9,849H.

Yet another attempt to increase processing power is to overlap the various subfunctions of instruction execution. The first step is to adopt pipe lining. These steps are a series of instructions By auto-blobbing, instruction execution is performed each clock time. , thereby increasing the processing power of the processor.

All of these methods for increasing throughput rely on inter-instruction arguments as described above. Because of their logical dependencies, they are designed for sequential instruction execution. logical subordination Due to the nature of the True simultaneous processing cannot be achieved, making processing easily compatible with elements. stomach.

An applied language is one in which each statement is essentially unrelated to each other and therefore its A network of processing elements designed to reduce application statements such as It differs from a command language in that it can be simultaneously realized by ing. An example of such an applied language processor is the US patent application of Bolton et al. No. 281,064 and 1-1a! U.S. Patent Application No. 28 of 7enmaier et al. 1.065. Both applications were filed on July 7, 1981. and has been assigned to the assignee of the present application. Such application languages are In the sense that it is not sequential in the eumanic sense, It is different from a command language. However, most professionals used today The gram library is written in a command language and has three d'' libraries, and Updates or yet another generation of data processing systems to be used to execute instruction languages must be made to do so.

One way in which processing height can be increased is for objects that do not depend on the results of previous processing. Recognize segments of code and route those segments through multiple processing elements. is to form a non-dependent sedance or matrix that can be processed simultaneously. . This of course destroys the operand's original value while it resides in memory. operands in such a way that operations can be performed on them without destroying them requires handling of the code. Different symbolic names can be used for this purpose with any data access. Can be specified to refer to an item.

The arrangement of such a queue of codes or symbols requires simultaneous processing by the processing unit. Adapt it to the following.

It is an object of this invention to provide an improved mechanism for generating dependent free instruction codes. It is to be.

Another object of the invention is to provide dependent free instruction code for execution by multiple processing elements. The goal is to provide a Still another object of the invention is to providing an improved mechanism for serving multiple processing elements in a simultaneous manner; That is.

Still another object of the invention is to eliminate redundant memory fetches and to The instruction code is a property that does not need to be reprocessed for processing such code in the series. The objective is to provide a mechanism for generating the code.

Summary of the invention To achieve the above-mentioned object, the present invention provides a string of object codes. and form them into higher-level tasks and define such tasks that are logically non-dependent. determine the sequence of screens so that they are executed separately , is directed to a cache mechanism for data processors. This cache The mechanism performs all memory accesses required by various tasks, and perform these tasks on local media where various data items are not stored. store along with a corresponding pointer or reference to the memory. This key The caching mechanism utilizes a symbol translation table, where tasks are of the queue, along with symbols representing various references or pointers to the queue. It is stored in the following manner. In this method, different data items are assigned separate tasks. can be assigned a separate symbol or symbol name for use with Limit dependencies between various tasks and control data changes.

A feature of the invention is that it provides a caching mechanism for a group of processing elements. , whose caching mechanism tasks strings of sequential object code. queues, each queue being logically independent of the others.

K1” 1 loss JU side The above objects and other objects, effects and features of this invention will be understood with reference to the drawings. It will become clearer from the detailed description given below.

FIG. 1 shows the object code string and A corresponding logically independent queue formed from that object code.

FIG. 2 is a schematic block diagram of a system according to the invention.

FIG. 3 shows the format of a queue created in accordance with the present invention.

FIG. 4 is a schematic block diagram of the symbol translation double module used in this invention. It is.

FIG. 5 is a schematic block diagram of processing elements used in the present invention.

FIG. 6 is a timing diagram illustrating the present invention.

General description of the invention In order to achieve the above-mentioned objects, effects and features, this invention has three different aspects. , i.e., improved code processing based on multiprocessing element 1, reference Has processing and parallel execution. In code processing, this invention first uses concatenation. preprocesses the instruction string, examines the relationships between a series of concatenated instructions, and The instructions are linked together to form a queue of dependent instructions. concatenated instructions The mechanism used to determine whether the following is a dependency on one concatenated instruction that provides output for the executed instruction. Once non- Once the dependencies are located, a queue is formed. Once a queue is formed , the mechanism according to the invention processes the entire queue in one step. That's effective. Requires several cycles to normally reprocess concatenated instructions is now done in one cycle, and the queue is used to execute a series of sequences. Does not need to be regenerated for the row.

Additionally, during the processing of the code, previously referenced and local to the processing element Certain operand references may be recognized. This applies to each reference and the item is in the processor's local memory. This is accomplished by scanning the translation table. If the reference is professional If the symbol does not reside in the processor's local memory, the invention , and each symbol corresponding to any queue is assigned to one processing element. appended there for subsequent transmission.

Once the corresponding holding matrices are formed, they are processed by multiple processing elements. Can be executed simultaneously.

In the design of today's processing systems, stack-oriented prolane stacks, Given a first-in-last-out stack, it can be used by certain high-level programming languages. Adapt recursive procedures and nested operations that can be used. Stack like this Given an oriented processor, it directs parts of the parent control program and processing system to Other routines that are recursive in nature, such as Algol 60, Can be written in level language. The specific processor module of this format is , B. arton et al. Patent No. 3.461.423, 3. ．． No. 546,677, and No. 3,548.384.

The stacking mechanism, a first-in, last-out mechanism, allows instructions and associated parameters to be is to manipulate the nested structures of a given high-level language in a reflective manner. So A stack such as is conceptually resident in main memory and is similar to the processor's stack l1es is made to contain a reference to the top data item in the stack. There is. In this way, many different stacks of data items are stored in memory. The processor uses them as the top of the stack registers that reside within the processor. The various stacks are accessed according to the address to the register, and the contents of the various stacks are can be addressed at different times by changes in .

If a processor is not provided with such a stacking mechanism, the processor A recursive type of language that uses general purpose registers to integrate them into the hardware stack. Although it is a mechanism, it is executed by addressing it.

A preferred embodiment of the invention executes a program written in a high-level recursive language. Although this invention is directed to such a stack-oriented processor for is a recursive language designed to perform different forms of high-level programming. It can also be used with other types of processors.

Once a program is written in this high-level language, it is compiler into a string of object code or machine language code. and its format is designed and controlled according to the specific processor design. . As mentioned above, most processors designed today are still VOnN eullan type, which is sequential in nature and subject to much discussion. Including logical dependence.

This invention provides dependent free code in the form of "decompiled" high-level language code. Reference is now made to FIG. 1 to generally illustrate how to provide .

The left column of Figure 1 is for calculating C[1,J]:=A[I,J]+B[I,J] does not represent a string of machine language code. This calculation is for many addresses. Since the string of machine language code shown on the left side of Figure 1 is performed in a sequence or series of

This string of codes is divided into four code groups or subsets. , each group is as shown by the block diagram in the central part of FIG. It is largely logically non-dependent from others. Generally, the mechanism of this invention performs the following processing. A logically independent store is Determine the end of the ring.

In this invention, the mechanism is a value call or a message as shown in the right column of FIG. memory, performs a retrieval, and returns the operator's holding matrix or data item (or local address for the data item). These operators and its data items are concatenated together and processed by processing elements in the manner described below. may be forwarded to Such concatenated instructions are hereinafter referred to as tasks. .

In the example of Figure 1, the four separate holding matrices are logically independent of the dependent concatenation instructions. group and executed simultaneously by separate processing elements as described below. can be carried out.

The string of code in the left column of Figure 1 is executed in a sequence of loops. The newly generated queue in the right column of Figure 1 should be regenerated. There is no need to be done. All that is required for each series of loops is to create new values and arrays. This means that the item is retrieved from memory. Also, the new pointer value must be assigned to the variable being stored.

Detailed description of the invention The processor system according to the present invention is shown in FIG. 0 is the operator's individual holding matrix and multiple small processing elements lia,b and a data reference to C and queue processing element 13a , each of which has its own local memory 12a. , , b and C and the local memory 13b, respectively. Cash The processing mechanism 10 communicates directly with main memory (not shown), and the individual processing elements It also communicates with main memory via a direct storage module 14.

Machine M410 consists of four units, and the four units 1~ Matrix task module 10a, instruction reference module 10b, symbol vA translation Mogicor IOC.

and job queue 10d. Here we describe the functions of these individual units. Briefly explain. individual strings of object code or machine language code The log is received from memory by the waiting task module 10a, and the waiting task module The module 10a receives each instruction serially and assembles them into a matrix of tasks. A buffer or cache memory for processing tasks, and the length of a task's queue is a series of due to logical dependencies between concatenated characters. Standby task module 10 a determines the sequence in which the linked group of instructions does not require the result of the previous 101 calculation. Contains sufficient decoding circuitry to Such a matrix of connected tasks is assembled, its operand reference becomes an instruction reference. The instruction reference module 10b stores the individual instructions. and perform any memory fetches required by the allocation symbol.

The waiting task module 10a also sends a queue number to the symbol translation module 10C. Assign.

The instruction reference module 10b has an absolute memory address that is logically maintained. It is an associative memory that determines whether the data is stored or not, and if it is not stored, the instruction standard Module 10b sends the address to main memory, stores the address, Access the memory by assigning a symbol to it. This associative memo Li then transfers the symbol with the corresponding task to the symbol translation module 10c. do. The symbol translation module 10c stores a pointer (local memory) for the symbol. address) and transfers its pointer to main memory, thereby can store data items in local memory. object During the first execution of a string of code, the queue for a sequence of instructions is symbolically translated It is formed in module 10c. While these queues form , individual tasks and pointers are transferred to job queue 10d.

The symbol translation module 10C may be referenced by the waiting task module 10a. This is a table-top memory having various matrix storage locations. these A memory location is a chain of instructions held in the local memory of a processing element. and a list of symbols for the item. When each holding matrix is read, Symbols that refer to the item referenced by the symbol are A read access to a lookup table containing pointers to actual storage locations. Used as a dress. Initial processing of the object code string in Figure 1 At the end, the job queue 10e contains each created queue and its The created queue is assigned to each processing item for concurrent execution by tasks and pointers. elements Ila, 11b, and 11c. On the other hand, for execution The individual data items needed are retrieved from main memory and stored in local memory. 12a, 12b, and 12c at appropriate storage locations. The location is accessed by a pointer in job queue 10d.

Completion of the first loop or execution of the object code completes all task processing. job queue 10d from symbol translation module 100 until processing is completed. A series of loops is executed by supplying the previously created holding matrix to It can be done.

The format when a queue resides in the job holding queue 10d in Figure 2 is It is shown in FIG. Each field read from left to right has a multiplication instruction, an addition command, dimming command, and 1. An integer followed by pointers to the J and C fields. This is Dex's command. These correspond to the first holding matrix (Qo) in Figure 1. , where an 8-bit literal becomes part of each multiply and add instruction.

The queue thus formed only holds instructions for future execution. the stack environment and its address and next line to be executed, Identifies the storage location of the column. Processing element with one matrix available for each step No other processing steps are required to process the code other than providing the Not possible.

The symbol translation module 10C of FIG. 2 is shown in more detail in FIG. In Figure 4 As shown, this module is a table lookup mechanism and has a matrix The columns of the symbol table 16 indicate the memory locations for the connected tasks and the commands in Figure 2. represents the symbolic name assigned by the command reference module 10b and also represents the corresponding symbol name. The corresponding rows correspond to each waiting line assigned by the waiting task module 10a of FIG. Represents the column number. As mentioned above, this way in the symbol translation module The queue formed is for each series of loops of computations to be performed as shown in Figure 2. Pointer in pointer table 17 for transfer to job queue 10d the printer is ready for access.

In Figure 4, the various symbols are indirect local memory references; That means items stored there can be given different pointers. Please be careful. This provides two advantages. Firstly, different points Any data can be created by renaming or assigning an interface to represent it. that the item is stored in one or more locations in local memory. It is. The second advantage is that any variable can be stored in one storage location and its pointer The data exits from there unchanged (while you can The result of the processing performed is another memory with the same symbolic name but a different pointer. This means that it can be stored in a location.

The individual treated elms 1- of FIG. 2 are shown in FIG. In summary, that are formed from multiple microprogrammed microprocessors. , the microprocessor is a commercially available one such as the Intel 8086. or they are disclosed in Faber et al., U.S. Pat. No. 3,983.539. Can be customized micro-programmed proreza . Since individual processors are made to perform different functions, they A special-purpose microprocessor that contains only the logic circuitry needed to perform each function. It may be a processor.

Each circuit 18 includes an arithmetic logic unit, a shift unit, a multiplication unit, an index a string processing unit, a string processor, and a decoding unit. moreover , the sequencing unit 19 receives instructions from the job holding matrix 10d in FIG. to access the microinstructions stored in the control store 2o. Control store? These microinstructions are supplied to each unit via the instruction bus IB, and are processed by the unit. Any status signals generated by the state bus CB are transferred via the status bus CB. Corresponding lo Data from the local memory is received on the A bus AB, and the executed results are sent to the B bus. Supplied to BB.

Returning to FIG. 1, the waiting task module 10a of FIG. formed by various instructions and their modules in a code string A more detailed explanation of higher level instructions or tasks is now provided.

As shown in the left column of Figure 1, the first fetch of the code string, the 8-bit value, and a multiplication instruction. They are used for the next task, i.e. the first task in the right column of Figure 1. The task of multiplying I by the literal value indicated by place is the instruction placed at the top of the sequence for addition and subtraction tasks. , the index instruction inserts a pointer to a disc libter in memory. This results in In this way, the first holding matrix. . is formed.

The array of Q is indexed after the instruction NXLV is executed after the name call instruction. are similar, except that they cause processing and data retrieval. in this way A second queue Q1 is thus formed. In the arrangement of the third queue Q2, There is an add instruction that destroys the value at the top of the stack. is calculated like this for A and B before the storage of memory destruction (STOD) The value added is added.

As can be seen from the block diagram in the center of Figure 1, the last two tasks of Q2 or Execution of the linked instructions is a calculation whose value is stored in local memory. oh We need the results of and Q. Its storage locations and their respective local memory are , a temporary index indicating whether the reference is actually stored there. given to the xx flag.

In this method, when the processing elements are processed in a concurrent manner, the rules of Q2 The process executes a second process before the required values are calculated and stored in local memory. It is possible to reach the or final addition task. Corresponding processing element detects that those values are not yet available, and when the values become available. It continues accessing those storage locations until it is reached.

The fourth holding matrix, or Q3, takes the value J and adds 1 to it, and tops the stack. the stack before performing a non-destructive store in memory, leaving the values in the stack intact. Insert the σ address into the The last four instructions retrieve the value K from memory. , compare it with the value J (LSEQ), and if the value K is greater than the value J, then the next instruction command, i.e. branching to false, reloads the program counter and Ching is repeated. On the other hand, the last instruction in the code string is the routine's It is an unconditional branch that results in termination.

Figure 6 is a timing diagram of queue execution times for individual queues; Each clock time for a task is represented by two numbers. first The number represents the particular loop or sequence being executed, the second number represents the command Represents a particular processing element that is executing an instruction. Resulting in an array of holding matrices The initial transmission of the code string and execution of the task takes approximately 17 clock hours. while a series of loops requires only 5 clock times to execute. and This is because tasks do not need to be completely reprocessed in QTM and IRM. This is because the individual dependent free queues are executed concurrently.

In general, the waiting task module handles tasks, waiting for these tasks, and queue executions. Execute simultaneous steps of instructions for line, tag prediction and branch correction. order Reference module performs renaming, symbol management and replacement functions do. The symbol translation module supports parallel access, pointer allocation and task allocation. give. Small processing elements allow unique processing elements to perform infrequent tasks. While used for functional parts of rows and strings, it is useful for performing frequent tasks. It will be provided for. The direct reference module 15 of FIG. It is set up for evaluation of reference.

lastly Takes the compiled object code and converts that code sequence to a higher level. form into a level task, and it executes the object code string before is logically unrelated to other holding matrices in the sense that it does not require the result of A mechanism for a data processor to form a queue of tasks such as It's here. In this way, the sequence of such queues is and may be supplied to non-dependent processing elements.

A symbol translation table is provided by which the data item is referenced and its A symbol can be assigned an arbitrary pointer to local memory, and that pointer cannot be changed. data items, such that the data items reside in one or more memory storage locations. A data item can also be stored in other stores as a result of operations on that item. It can remain in memory while being stored in a location.

Embodiments of this invention have been described, but depart from the spirit of the claimed invention. It will be obvious to those skilled in the art that changes and modifications can be made without deviating from the Will.

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Claims (1)

[Claims] 1. Data for executing instruction code including operator and memory address a data processing system that forms logically independent strings and then means for forming dependent operators into a logically independent matrix; A storage for storing the logically independent holding matrices.A storage for storing the logically independent holding matrices. and a plurality of processing means each receiving a plurality of processing means. 2. The forming means is 1. In response to the instruction code in a sequential manner, the operation Determines when a factor does not require the results of previous operations and thus exhibits logical non-dependence. , and forming said logically independent string and subsequently forming said logically dependent string. Claim 1, further comprising means for forming operators into logically independent queues. System described. 3. The data processing system includes a main memory and receives the memory address. and further comprising main memory addressing means for retrieving data from said main memory. The system according to item 2 of the scope. 4. Each of the processing means includes local storage and is connected to the main memory. is used to transfer the local memory address to said memory, thereby memory so that the retrieved data can be transferred to the local memory. Claim 3 further comprising local storage address means for system. 5. The receiving means receives pairs of operators forming a specific logically independent matrix. said local memory address to a corresponding string. The system according to item 4 of the scope of demand. 6. Receive and execute sequential code including operators and memory addresses A processing method in a data processing system for receiving said sequential code; Determine when an operator does not need the results of a previous operation that exhibits logical nondependence. , Logically independent strings and subsequent logically dependent operators into non-dependent queues and separate ones of said queues for simultaneous execution. , methods of transfer to different individual processing means. 7. The data processing system includes a main memory, receives a main memory address, and receives a main memory address. 7. The method of claim 6, further comprising retrieving data from the main memory. Law. 8. Each of said processing means includes local storage and has a local memory address. transfer the retrieved data to the main memory, thereby causing the main memory to transfer the retrieved data to the main memory. further comprising: being capable of being transferred to said mouth--calm memory; The method according to claim 7. 9. the local memory addresses to form a specific logically independent queue; Claim 8 further comprising: providing a corresponding string of operators. The method described in section. 10. The data processing system includes a job queue, and the data processing system The dependent holding matrix and the corresponding local memory address are processed by the processing means of said sides. further comprising forwarding to the job queue for subsequent distribution to the job queue; The method described in claim 9.