JPS6313189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display driving device, and in particular, the present invention relates to a display driving device, which is provided in an electronic cash register (ECR), and which displays a plurality of digit characters in a dot matrix type display, as well as a segment type display. The present invention relates to a display driving device that displays a multi-digit numerical value in a segment format on a device.

The ECR is provided with an operation confirmation display section so that the operator can confirm the unit price of the entered product and its total price. This operation confirmation display is provided on the front of the ECR. Additionally, ECR
A customer display section is provided at the top of the main body so that the customer can check the registered details. This customer display section is not necessarily required, but is a so-called optional display section that is installed later according to the user's request. In such ECRs that have two display sections, relatively inexpensive ones display the same content on both display sections, and it is recommended that the display drive device be shared in order to reduce costs. Common.

FIG. 1 is a schematic block diagram of a display driving device included in a conventional ECR. Referring to FIG. 1, the configuration and operation of a conventional display driving device will be described. Display data and data representing the number of digits thereof are provided to the controller 1 from a CPU (not shown). This controller 1 outputs a display digit designation signal based on the display data and digit number data given from the CPU, and also sends a segment code to the numerical value to be displayed in the display digit designated by the display digit designation signal. Output as data. The display digit designation signal and segment code data output from the controller 1 are latched by a latch circuit 2. Latch circuit 2 is, for example, 8243 (Intel)
etc. are used. The display digit designation signal latched by the latch circuit 2 is applied to the decoder 3 and decoded. The output of this decoder 3 is the digit driver 4
given to. Digit driver 4 drives one of the display digits of segmented displays 5 and 8. The segment type display 5 has a display area of 16 digits and serves as a display section for customers. Further, the segment type display 8 has a display area of 20 digits and serves as a display section for confirming operation.

On the other hand, the segment code data latched by the latch circuit 2 is given to the segment driver 6. The segment driver 6 drives the segment of the designated display digit of each of the segment type displays 5 and 8. Furthermore, a segment signal representing a symbol such as a comma is output from the latch circuit 2,
Segment driver 7. The segment driver 7 drives segments such as commas in designated display digits of the segment type displays 5 and 8.

As mentioned above, in the conventional ECR, the two segment type displays 5 and 8 are each commonly controlled. By the way, although the segment type displays 5 and 8 are suitable for displaying numbers,
Characters other than numbers cannot be displayed. In particular, in recent ECRs, dot matrix displays are being used to display various messages to operators. However, this dot matrix type display is more expensive than the segment type display, so the dot matrix type display is used as the display part for operation confirmation, and the conventional segment type display is used as the display part for customers. used. Since the data to be provided is different between such a dot matrix type display and a segment type display, they cannot be used in a conventional display driving device as shown in FIG.
That is, display driving devices must be provided separately for the dot matrix type display and the segment type display, which increases the number of parts and increases the cost.

Therefore, the main object of the present invention is to provide a display driving device that can use peripheral circuits in common and can display various data on a dot matrix type display and a segment type display. .

To summarize this invention, character code data representing a character to be displayed on a dot matrix type display by a data generating means such as a CPU, and numerical code data representing a numerical value to be displayed on a segment type display. , a character, and a command signal including digit number data representing the number of displayed digits of a numerical value to the controller. The controller stores character code data and numerical code data, and outputs a display digit designation signal every time a command signal is output, and also outputs the character code data and numerical code of the character to be displayed in the specified display digit. Output data sequentially. Then, based on the display digit designation signal, the corresponding display digits of the dot matrix type display and the segment type display are commonly driven, and the corresponding character data is output based on the character code data to display the dots. Characters are displayed on a matrix type display, and numerical values are displayed on corresponding display digits of a segment type display based on numerical code data.

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 2 is a schematic block diagram of one embodiment of the invention, and FIG. 3 is a detailed block diagram of the same.

Next, the configuration of an embodiment of the present invention will be described with reference to FIGS. 2 and 3. CPU13
and controller 1 are connected by a data bus, a control bus, and an address bus. Furthermore, a reset signal and a clock signal are given to the controller 1 from the CPU 13. Controller 1 has buffer pointers 101 and 102.
RAM103, timer 104, and digit counter 105
including. The buffer pointers 101 and 102 are
This is for specifying the address of RAM 103. The timer 104 is used to issue a timer interrupt at fixed time intervals (640 μsec), and is used to count time through program processing.

The digit counter 105 is for counting the displayed digits of the dot matrix type display 12 and the segment type display 5. The strobe signal PROG is commonly applied from the controller 1 to the latch circuits 2 and 9, and the enable signal DCS0 is applied to the latch circuit 2.
DCS1 is applied to the latch circuit 9. These enable signals are for activating latch circuit 2 and latch circuit 9 individually. Furthermore, from controller 1 to the data bus
Character code data and digit number data are supplied to the latch circuit 2 via DBs 20-23.
Also, part of the segment signals DSEG4 to DSEG6 are given from the controller 1 via this data bus. The latch circuit 2 provides 4-bit digit designation signals DS0 to DS3 to the digit decoder 3 based on the digit number data. This digit decoder 3 is supplied with an enable signal CE from the latch circuit 2. The digit decoder 3 outputs a signal for commonly specifying the display digit of each of the dot matrix type display 12 and the segment type display 5 based on the digit designation signal, and sends the designation signal to the driver 41, Give to 42.

The driver 41 is a dot matrix display 12
The driver 42 drives the display digits of the segment type display. The dot matrix type display 12 includes a dot matrix of 16 digits with 5 columns in the horizontal direction and 7 rows in the vertical direction.
It is possible to display numerical values and other characters. Symbol data such as a comma is provided from the latch circuit 2 to the driver 10. driver 10
drives commas and the like on the dot matrix display 12 based on the data. Further, character code data is outputted from the latch circuit 2 and applied to the character ROM 111. This character ROM 111 stores various character data composed of 5×7 dots, and when character code data is given, it outputs the corresponding character data using it as an address signal. This character data is given to driver 112. The driver 112 drives the dots in the designated display digits of the dot matrix display 12 to display the corresponding characters.

On the other hand, the latch circuit 9 supplies a segment signal such as a comma to the segment driver 7. The segment driver 7 drives the segment corresponding to the comma of the designated display digit of the segment type display. Furthermore, the latch circuit 9 provides the segment driver 6 with 3-bit segment signals DSEG4 to DSEG6. This segment driver 6 is supplied with 4-bit segment signals DSEG0 to DSEG3 from the controller 1. The reason why only 4 bits of the segment signal are given directly from the controller 1 to the segment driver 6 and the 3-bit segment signal is given from the data bus to the segment driver 6 via the latch circuit 9 is because of the number of terminals on the controller 1. This is because only the 4-bit segment signal is output directly and the rest are output from the data bus. The segment driver 6 drives the segment of the designated display digit of the segment type display 5 based on the applied 7-bit segment signal.

4 to 6 are flowcharts for explaining the specific operation of an embodiment of the present invention. In particular, FIG. 4 shows the processing routine of the CPU 13, and FIG. 5 shows the main routine of the controller 1. shows,
FIG. 6 shows the interrupt processing routine of the controller 1. FIGS. 7 and 8 are waveform diagrams of various parts in FIG. 3.

Next, with reference to FIGS. 2 to 8, specific operations of an embodiment of the present invention will be described.

First, the CPU 13 executes operations according to the processing routine shown in FIG. i.e. CPU
13 sets an initial command in step (abbreviated as SP in the figure) 1. This initial command includes, for example, a signal representing the number of digits of data to be displayed on the dot matrix display 12 and the segment display 5. Furthermore, the CPU 13 outputs character code data representing the character to be displayed on the dot matrix display 12 in step 2. Since the dot matrix display 12 is capable of displaying 16 digit characters, in step 3
Determine whether 16 digits of data have been output. 16
If the data for the next digit has not been output, then in step 2, the character code data for the next digit is output. This operation is repeated to sequentially output 16 digits of character code data. After outputting the 16-digit character code data, in step 4, numerical code data representing the numerical value to be displayed on the segment type display 5 is output. And step 5
At step 4, it is determined whether or not eight digits of data have been output, and if eight digits of data have not been output, the next digit of data is output again at step 4. This operation is repeated to output eight digits of numerical code data to be displayed on the segment type display.

On the other hand, controller 1 in step 6
The RAM 103 is initially reset, and in step 7 it is determined whether data or a command signal has been received. Once the data is received, step 8
Then, in step 9, the received data is stored in the RAM 103. That is, when character code data is received, the RAM 103 addressed by the buffer pointer 101
If you store the character data in the area and receive the numerical code data, the buffer pointer becomes 1.
The numerical code data is stored in the area of RAM 103 designated by 02. And the steps
Buffer pointer 101 or 10 at 10
Add 1 to 2 and return to step 7. Repeating this operation, the character code data or numerical code data output from the CPU 13 is sequentially transferred to the RAM.
Store in 103.

When the initial command is output from the CPU 13, it is determined in step 8 that it is not data, and in step 11 it is determined whether it is an initial command. If it is not the initial command, other command processing is performed in step 13. If it is an initial command, step
At step 12, the timer 104 of the controller 1 is enabled. Thereafter, the interrupt processing routine is executed every 640 μsec.

First, in step 14, the controller 1 sets the chip select signal DCS0 to L to activate the latch circuit 2. When the chip select signal DCS0 becomes L level, the latch circuit 2 changes the CE signal to a high level in step 15 to enter a blanking state. In other words, the output of the digit designation signal from the digit decoder 3 is prohibited. In step 16, the controller 1 supplies the count value of the digit counter 105 to the latch circuit 2 via the data bus as a digit designation signal. depending on,
The latch circuit 2 provides a digit designation signal to the digit decoder 3. Digit decoder 3 decodes the digit designation signal and provides the digit designation signal to drivers 41 and 42. The driver 41 drives the first digit of the dot matrix display 12. Driver 42 also drives the first digit of the segmented display.

In step 17, the controller 1 reads 8-bit character code data from the area of the RAM 103 designated by the buffer pointer 101. This character code data is applied to the latch circuit 2 via the data bus. Latch circuit 2
is put into a writing state by the controller 1 and stores the 8-bit character code data.
Then, the latch circuit 2 is placed in a read state by the controller 1, and in step 17 outputs the lower 4 bits of the 8-bit character code data, and then outputs the upper 4 bits of data. At the same time, data indicating commas, cursors, etc. is output from latch circuit 2, and driver 1
0, a dot corresponding to a comma or a cursor in the dot matrix 12 is driven.
The character code data output from the latch circuit 2 is given to the character ROM 111. In response, the character ROM 111 outputs character data of 5×7 dots corresponding to the character code data as an address signal.
This character data drives the dots of designated display digits on the dot matrix type display 12 via the driver 112. As a result, the specified display digit of the dot matrix display 12 is
Characters are displayed in the form of 7 dots.

In step 20, the controller 1 sets the chip select signal DCS0 to the H level and sets the chip select signal DCS1 to the L level. Thereby, latch circuit 2 is disabled and latch circuit 9 is enabled. Then, the controller 1 outputs the data of the upper 4 bits of the segment signal via the data bus, and also outputs the segment signal representing a comma.
It also outputs DPC. This segment signal DPC is given to the segment driver 7. The segment driver 7 drives the segment corresponding to the comma of the segment type display 5. In addition, the latch circuit 9
The upper 4 bits of data DSEG4 to DSEG6 of the segment signal latched by are given to the segment driver 6. Further, in step 22, the controller 1 outputs data DSEG0-3 of the lower 4 bits of the segment signal and supplies it to the segment driver 6. Based on the given segment data DSEG0 to DSEG6, the segment driver 6
Numerical values are displayed in segments in the display digits designated by the driver 42 of the segment type display 5.

At step 23, the chip select signal DCS
0 to L level and DCS1 signal to H level. Thereby, latch circuit 2 is activated and latch circuit 9 is deactivated. Furthermore, in step 24, the enable signal CE applied to the digit decoder 3 is set to L level. As a result, the blanking state is canceled and characters and numerical values are displayed on the dot matrix display 12 and the segment display 5, respectively. In step 25, controller 1 controls digit counter 10.
Add 1 to 5. The next digit is thereby selected and the process returns to the main routine shown in FIG. Similarly, character data and numerical data are displayed alternately on the dot matrix display 12 and the segment display 5 in a time-sharing manner.

As described above, according to this embodiment, character code data is stored in the latch circuit 2, numerical code data is stored individually in the latch circuit 9, and the dot matrix is Since the shape display 12 and the segment display 5 are each driven in common, even if the display modes of the dot matrix display 12 and the segment display 5 are different, the digit designation circuit remains the same. Can be used commonly. Therefore, the number of peripheral circuits for display can be reduced and the configuration can be simplified.

In the above embodiment, the controller 1 outputs a 7-bit segment signal. However, the present invention is not limited to this, and the controller 1 may output numerical data based on a BCD code, and the segment decoder may convert this into a 7-bit segment signal for use.

As described above, according to the present invention, even when characters and numerical values are individually displayed on a dot matrix type display device and a segment type display device having different display modes, the digit designation circuit can be used in common. Since it is used, the number of parts can be reduced, the structure can be simplified, and the cost can also be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a display driving device which is the background of the present invention. FIG. 2 is a schematic block diagram of one embodiment of the present invention. FIG. 3 is a similar concrete block diagram. FIG. 4 is a flow diagram showing the processing routine of the CPU. FIG. 5 is a flow diagram showing the main routine of the controller.
FIG. 6 is a flow diagram showing the interrupt processing routine of the controller. FIGS. 7 and 8 are waveform diagrams of various parts in FIG. 3. In the figure, 1 is a controller, 2 is a latch circuit, 3 is a digit decoder, 4, 41, 42, 10 are drivers, 9 is a latch circuit, 12 is a dot matrix type display, and 13 is a CPU.

Claims (1)

[Scope of Claims] 1. A display driving device including a dot matrix display that displays a multi-digit character in a dot format and a segment display that displays a multi-digit numerical value in a segment format, data generating means for generating a command signal including character code data representing a character to be displayed, numerical code data representing a numerical value to be displayed, and digit number data representing the character and the number of digits to be displayed of the numerical value; The character code data and the numerical code data output from the means are stored, and the dot matrix type display and the segment type display are stored at predetermined intervals in response to the output of a command signal from the data generating means. a display digit designation signal that designates the display digit of the display;
A controller that sequentially outputs character code data and numeric code data of characters to be displayed on each designated display digit; Digit driving means for commonly driving the corresponding display digits of the segment type display, storing a plurality of character data in advance, and driving the corresponding display digits in response to the character code data given from the controller; dot driving means for outputting character data and displaying a character based on the character data on a display digit of the dot matrix type display driven by the digit driving means; and numerical code data output from the controller. A display driving device comprising segment driving means for driving a segment of a display digit of the segment type display driven by the digit driving means to display a numerical value. 2. The display driving device according to claim 1, wherein the controller outputs a segment signal as numerical code data at every predetermined time.