JPS63131380A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To correct deviation of bit of a data attended with parallel readout by generating plural data subject to phase shift and selecting a synchronized data among them in a magnetic disk device applying parallel readout of plural data. CONSTITUTION:The titled device is provided with plural shift registers 11, 21 outputting plural data subject to phase shift simultaneously for plural number of times to a data sent from a read means, pattern decoders 15, 25 detecting a synchronizing data, counter 16, 26 counting a clock signal corresponding to a phase difference between the phase of the synchronizing data and the phase of a reference synchronizing data, and selectors 18, 28 selecting the data having a phase coincident with the phase of the reference synchronizing data based on the output of the counters among the plural data subject to phase shift. Then plural data whose phase are deviated to the data as to each readout data are generated and the data having a synchronizing bit whose phase are coincident with that of the synchronizing bit being a reference are selected among them. Thus, the bit deviation of parallel readout data is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read circuit for a magnetic disk device that reads data in parallel.

[Already required]

In a magnetic disk device that reads a plurality of pieces of data in parallel, the present invention generates a plurality of phase-shifted data and selects synchronized data from among them, thereby reducing the bit shift of data due to parallel reading. This is so that it can be corrected.

[Conventional technology]

Conventionally, this type of magnetic disk device includes one or more magnetic disks, the same number of continuous beds, and the same number of continuous circuits,
Each successive output circuit read data in parallel, and sent the parallel successive data as is to the host device.

[Problem that the invention seeks to solve]

Such conventional magnetic disk drives output parallel successive data as is to the host device, so if the characteristics of the elements in each successive circuit vary, each bit of the parallel successive data will shift, making it impossible to read the correct data. There are drawbacks.

For example, if writing is performed in parallel with 2 bits, and two parallel bits at the same time constitute one piece of data at that time (hereinafter referred to as a parallel 2-bit data), then the write parallel 2-bit data is In chronological order “0.3.1.
0.0''. That is, when this write parallel 2-bit data is arranged in chronological order for each bit, the write upper bits are rO,, L Olo, 0'', and the write lower bits are [0, ■, 1.0... It is 0. Assume that when this written parallel 2-bit data is read, the succeeding lower bits are read out one bit later than the successive upper bits. In other words, the consecutive high-order bits arranged in chronological order are "
0.1, Olo, 0'', and the consecutive lower bits are ``0.
0.1.1.0'', the read upper bit and successive lower bit at the same time will be 1, similar to the write parallel 2-bit data.
Therefore, the successive parallel 2-bit data arranged in chronological order becomes [0, 2, 1, 1, O'', and data different from the written parallel 2-bit data is read out.

SUMMARY OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks and to provide a magnetic disk device capable of correcting bit shifts in parallel successive data.

[Means for solving problems]

The present invention provides a magnetic disk drive equipped with a reading means for reading a plurality of pieces of data having synchronous data in parallel.
a plurality of shift registers that output each of a plurality of data whose phases are shifted simultaneously a plurality of times with respect to each of the data sent out from the reading means; a pattern decoder that detects synchronous data; and a pattern decoder that detects synchronous data; a counter that counts clock signals corresponding to the phase difference between the phase of the data and the phase of the reference synchronization data; and based on the output of this counter, the phase-shifted plurality of data having a phase matching the phase of the reference synchronization data are counted. The present invention is characterized by comprising a selection means for selecting from among the data.

[Effect]

When data is read in parallel with a magnetic disk device, bit shifts may occur in the read data. In the present invention, for each read data, a plurality of data whose phases are shifted from this data are generated. The phase position of the synchronization bit attached to this data is detected, and the phase shift with respect to the reference synchronization bit is counted. Based on this count value, data having a synchronization bit whose phase matches that of the reference synchronization bit is selected from the data generated by shifting the phase.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing chart of signals of each part shown in FIG.

First, the configuration of this embodiment will be explained based on FIG.

The shift register circuit 11 is connected to a lower circuit (not shown) by a read data signal 1a and a write enable signal 3.

The shift register circuit 21 is connected to a lower circuit (not shown) by a read data signal 2a and a write enable signal 3.

The pattern decoder circuit 15 receives the delayed data signal 1b.
Shift register circuit 1 with delayed data signal IC
1 and is connected to a write enable signal 3 to a lower circuit (not shown). The pattern decoder circuit 25 is connected to the shift register circuit 21 by the delayed data signal 2b and the delayed data signal 2c, and is connected to a lower circuit (not shown) by the read enable signal 3. Gate circuit 31
is connected to the pattern decoder circuit 15 by the pattern detect signal 1f, and connected to the pattern decoder circuit 25 by the pattern detect signal 2f. The counter circuit 16 receives the pattern detect signal If from the pattern decoder circuit 1.
5 and is connected to the gate circuit 31 by the detect signal 3j. The counter circuit 26 is connected to the pattern decoder circuit 25 by the pattern detect signal 2f, and connected to the gate circuit 31 by the detect signal 3j. Counter decoder circuit 17 detects counter circuit 1 with count signal 1g.
6 and is connected to the gate circuit 31 by the detect signal 3j. The counter decoder circuit 27 is connected to the counter circuit 26 with the count signal 2g and detects the detect signal 3g.
j is connected to the gate circuit 31. The selector circuit 18 receives a delayed data signal 1e and a delayed data signal 1d.
Shift register circuit 1 with delayed data signal IC
1, is connected to the count decoder circuit 17 by the selector signal 1h, and is connected to a higher-order circuit (not shown) by the data signal 1i.

The selector circuit 28 is connected to the shift register circuit 21 with the delayed data signal 2e, the delayed data signal 2d, and the delayed data signal 2c, and is connected to the count decoder circuit 27 with the select signal 2h, and the data signal 21
It is connected to a higher-level circuit (not shown).

Next, it is assumed that the synchronized data of each bit is "1.1" in chronological order, the writing and reading are 2-bit parallel, and the writing 2-bit parallel data is [3, 3, 0, 0, 0, 1 ,2,3,0,2,1,3,
0, 0, 0, 0, J, the read data signal 1a is the read upper bit, the read data signal 2a is the successive lower bit, and the read data signal 2a is delayed by 2 bits compared to the read data signal 1a. , that is, the write upper bit of write 2-bit parallel data is "l, 1.0.0.0.0.1., L Oll, 0.1
0.0.0.0", write lower bit is "l, 1.0.0.0.1, Oll, 0.0.1.1.
0.0.0.0'', but the read data signal 1a, which is the lower bit, continues.
is “1.1, Olo, 0.0.1.1.0, ■, 0.1.
0.0.0.0'', and the read data signal 2a, which is the lower bit, continues to be ``0.0.0.0''.
．． 1.1.010.0.1.0.1.0.0.1.1.
0.0,'' the operation will be explained based on FIGS. 1 and 2.

When the read enable signal 3k becomes active, the shift register circuit 11, the shift register circuit 21, the pattern decoder circuit 15, and the pattern decoder circuit 25 start operating. The shift register circuit 11 delays the read data signal 1a (see FIG. 2 1a) by 1 bit and outputs it as the delayed data signal 1b (see FIG. 2 1b), and delays the delayed data signal 1b by 1 bit and outputs it as the delayed data signal 1c. The delayed data signal lc is delayed by 1 bit and output as the delayed data signal 1d), the delayed data signal 1d is delayed by 1 bit and output as the delayed data signal 1d).
e (see FIG. 2, 1e). Similarly, the shift register circuit 21 receives the read data signal 2a (FIG. 2A).
(see Figure 2 2b) and output it as the delayed data signal 2b by delaying it by 1 bit.
The delayed data signal 2c should be delayed by 1 bit and output as the delayed data signal 2c (see FIG. 2, 20), and the delayed data signal 2c should be delayed by 1 bit and output as the delayed data signal 2d.
(see Figure 2d), delayed data signal 2d is delayed by 1 bit and output as delayed data signal 2e (see Figure 2).
8). The pattern decoder circuit 15 monitors the delayed data No. 13 lb and the delayed data signal IC, and when these signals become synchronous data, that is, rt, IJ, activates the pattern detect signal 1f.
This active state is maintained (see FIG. 2 1f).

Similarly, the pattern decoder circuit 25 monitors the delayed data signal 2b and the delayed data signal 2c, and when these signals become synchronized data, that is, "1.1", pattern detect (makes the i signal 2f active, The gate circuit 31 maintains the active state (see FIG. 2 2f). When the pattern detect signal 1f and the pattern detect signal 2f become active, the gate circuit 31 activates the detect signal 3j (see FIG. 2 3j).Counter circuit 16 is reset while the pattern detect signal If is inactive, and starts counting when the pattern detect signal If becomes active,
When the detect signal 3j becomes active, it stops counting, holds the count value, and outputs it as the count signal 1g (see FIG. 2, 1g). Similarly, the counter circuit 26
is reset while the pattern detect signal 2f is inactive, starts counting when the pattern detect signal 2f becomes active, stops counting when the detect signal 3j becomes active, holds the count value, and outputs the count signal. Output to 2g (Figure 2 2g
reference). When the detect signal 3j becomes active, the count decoder circuit 17 outputs a select signal 1h determined by the value of the count signal 1g (see FIG. 2, 1h). Similarly, when the detect signal 3j becomes active, the count decoder circuit 27 outputs a select signal 2h determined by the value of the count signal 2g (see FIG. 2, 2h).

The selector circuit 18 outputs any one of the delayed data signal 1c, the delayed data signal 1d, and the delayed data signal 1e as the data signal 11 based on the select signal 1h.

That is, the delayed data signal 1e is the data signal 11.
(See FIG. 2, 11). Similarly, the selector circuit 28 converts any one of the delayed data signal 2c, the delayed data signal 2d, and the delayed data signal 2e into the data signal 2 based on the select signal 2h.
Output to 1. That is, the delayed data signal 2c is output as the data signal 21 (see FIG. 21).

As described above, even if a bit shift occurs during reading, read data with the bit shift corrected is output as the data signal 11 and the data signal 21.

In addition, even if you prepare the necessary number of shift register circuits, pattern decoder circuits, counter circuits, counter decoder circuits, and selector circuits to prevent bit shift for any synchronous data or any number of parallel successive data, it is still possible to The invention can be put into practice.

〔Effect of the invention〕

As described above, the present invention corrects the phase shift of parallel successive data that has caused a phase shift, so it has the effect of supplying normal parallel successive data and increasing the reliability of the successive data. The circuit of the present invention has the advantage that it can be constructed with simple hardware without requiring complex memory means.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the apparatus according to the embodiment of the present invention. 11.21...Shift register circuit, 15.25...
・Pattern decoder circuit, 16.26... Counter path, 17.27... Counter decoder circuit, 18.2
8... Selector circuit, 31... Gate circuit, 3k.
...Write enable signal, 1a, 2a-read data signal, lb, 2b, 1c, 2c, 1d, 2d, le, 2
e-delayed data signal, 1f, 2f... pattern detect signal, 3j... detect signal, 1g, 2
g...Count signal, lh. 2h...Select signal, li, 2i...Data signal. Figure 2 shows the operation of the example in 3.

Claims (1)

[Claims] (1) In a magnetic disk drive equipped with a reading means for reading out a plurality of pieces of data having synchronous data in parallel, a plurality of pieces of data whose phase is shifted simultaneously multiple times for each piece of data sent out from the reading means. a pattern decoder that detects synchronized data, a counter that counts clock signals corresponding to the phase difference between the detected synchronized data and the reference synchronized data; A magnetic disk drive characterized by comprising: selection means for selecting data having a phase matching the phase of the reference synchronization data from among the plurality of phase-shifted data based on the output of a counter.