JP3775145B2 - Digital signal recording device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital signal recording apparatus for recording digital data such as a digital video signal on a magnetic tape using a pair head composed of a plurality of adjacent magnetic heads.
[0002]
[Prior art]
A method of recording digital data while simultaneously forming a plurality of tracks on a magnetic tape using a plurality of magnetic heads arranged adjacent to each other on a rotating drum is known. In Japanese Patent Laid-Open No. 11-134742, when digital data recorded on a magnetic tape is reproduced in this way, tracking control is performed at a high speed due to a difference in reproduction timing of reference signals in two magnetic heads constituting a pair head. Technology is shown.
[0003]
FIG. 4 is a diagram for explaining the principle of such tracking control. FIG. 4A shows two magnetic heads constituting a pair head, that is, + azimuth head and −azimuth head are + azimuth track and −azimuth, respectively. FIGS. 5B and 5C are diagrams showing a state in which a track shift, that is, a tracking shift, has occurred in the + azimuth head and the −azimuth head, respectively.
[0004]
Normally, between two adjacent tracks, the head gap of the magnetic head is shifted by a predetermined angle in the + and − directions with respect to the direction orthogonal to the head trace direction, as shown in FIG. Are doing different azimuth records.
[0005]
In the tracking control shown here, when the signal is reproduced from the magnetic tape on which the azimuth recording is performed between the adjacent tracks as described above, the reproduction timing of the reference signal according to the tracking deviation amount is + azimuth head and −azimuth head. As shown in FIG. 4 (a), if the + azimuth head and the −azimuth head accurately trace the + azimuth track and the −azimuth track, respectively, The reference signal of the azimuth track is reproduced at the same timing by the azimuth head and the azimuth head, respectively.
[0006]
On the other hand, as shown in FIG. 4B, when a trace shift occurs, the reference signal for the −azimuth track is reproduced after the reference signal for the −azimuth track is reproduced. When a trace deviation occurs as shown in c), after the reference signal for the + azimuth track is reproduced, the reference signal for the −azimuth track is reproduced.
[0007]
Therefore, from which of the magnetic heads of the paired heads the reference signal is reproduced first, and the time from when the reference signal is reproduced by one magnetic head until the reference signal is reproduced by the other magnetic head By using a counter or the like to count, it becomes possible to directly obtain the tracking correction amount, and high-speed tracking control can be performed.
[0008]
Actually, since each track is formed in an inclined manner, as shown in FIG. 5, there is a deviation in the track formation timing between the + azimuth head forming the pair head and the − azimuth head. -When starting playback of the azimuth track after starting playback, even if the + azimuth head and-azimuth head accurately trace the + azimuth track and-azimuth track, respectively, the playback timing of the reference signal is shifted. In such a case, the time from when the reference signal is reproduced by the azimuth head to the time when the reference signal is reproduced by the azimuth head is + track formation timing between the azimuth head and the azimuth head Needless to say, tracking control is performed so as to match the amount of deviation.
[0009]
However, since the tracking control method described above performs tracking control using the reproduction timing of the reference signal, accurate tracking control cannot be performed if there is a deviation in the recording position of the reference signal.
[0010]
FIG. 6 is a diagram for explaining the configuration of a conventional digital signal recording apparatus for recording digital data using a pair head, and FIG. 7 is a diagram showing the recording operation. FIG. 6 shows only the recording system of one magnetic head in the pair head mounted on the rotary head. When the pair head is constituted by two adjacent magnetic heads, the configuration shown in FIG. There are two. Here, it is assumed that two such pair heads are provided on the rotating drum so as to face each other at approximately 180 degrees (a total of four magnetic heads), and there are four configurations shown in FIG.
[0011]
In FIG. 6, reference numeral 1 denotes a frequency-dividing circuit that divides a clock by 5 from an input clock and outputs the divided clock. Reference numeral 2 denotes a head switch pulse that is generated based on a pulse that is synchronized with the rotational phase of a rotating drum (not shown). This is a data processing unit that receives recording data and performs processing such as 24-25 conversion on the basis of the divided-by-5 clock from the divided-by-5 circuit.
[0012]
Reference numeral 3 denotes a parallel-serial conversion unit that receives the recording data that has been processed by the data processing unit 2 in parallel and serially outputs it based on a clock. The recording data output from the parallel-serial conversion unit 3 is recorded on the magnetic tape via the magnetic head.
[0013]
[Problems to be solved by the invention]
However, in the digital signal recording apparatus configured as described above, as shown in FIG. 7, the time from the switching timing of the head switch pulse to the actual signal recording start timing is not constant, and the signal recording by the + azimuth head is performed. Since the time from the start timing to the start timing of signal recording by the azimuth head is not constant, there is a problem that accurate tracking control cannot be performed.
[0014]
That is, the head switch pulse and the recording data are input to the data processing unit 1 shown in FIG. 6, the recording data is processed with the divided-by-five clock generated from the clock, and the parallel-serial conversion unit 3 records based on the clock. Data is serially output. However, since the processing in the data processing unit 2 is processing by a divide-by-5 clock, there is a possibility that the start timing of signal recording is shifted within the range of the pulse interval of the 5-minute cycle clock. .
[0015]
Although not shown here, the switching timing of the head switch pulse of the + azimuth head and the switching timing of the switch pulse of the −azimuth head are asynchronous with the pulse of the divide-by-5 clock. The time from the start of recording to the start of signal recording by the azimuth head is not constant.
0016
[Means for Solving the Problems]
In order to solve the above problems, a digital signal recording apparatus according to the present invention provides:
A digital signal recording apparatus for recording digital data while simultaneously forming first and second inclined tracks on a magnetic tape using first and second magnetic heads arranged adjacent to each other on a rotating drum. ,
N-divided clock output means for generating an n-divided clock divided by n from a recording clock for recording the digital data;
A pulse synchronized with the rotation phase of the rotating drum, recording data, and an n-divided clock from the n-divided clock output means are input, and the recording data is signal-processed with the n-divided clock and output. Data processing means;
A pulse synchronized with the rotation phase of the rotating drum and the n-divided clock are input, and a delay amount corresponding to the timing difference between the input timing of the pulse and the switching timing of the n-divided clock is determined and output. A delay amount determining means;
Respectively provided a recording system circuit Ru and a delay means for applying a delay corresponding to the delay amount determined by the delay determining means to the recording data to said first and second magnetic heads,
The recording clock and the n-divided clock are shared by the recording system circuits of the first and second magnetic heads,
The first and second magnetic heads use the first and second magnetic heads so that the recording data output from the delay means of the respective recording system circuits have different azimuths on the first and second tracks. In this case, recording is performed while simultaneously forming tracks.
[0017]
In addition to the above-described configuration, the delay amount determining means includes a first time from a pulse timing synchronized with a rotation phase of the rotating drum to a recording start timing by the first magnetic head , and a delay time of the rotating drum. The delay amount so that the second time from the pulse timing synchronized with the rotation phase to the recording start timing by the second magnetic head is constant with an error corresponding to one clock of the recording clock. it is characterized in determining the.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram for explaining a digital signal recording apparatus according to the present invention. Components identical to those of the conventional digital signal recording apparatus shown in FIG. 6 are denoted by the same reference numerals. In the digital signal recording apparatus according to the present embodiment, pair heads composed of two adjacent magnetic heads are arranged one by one on the rotating drum so as to face each other at approximately 180 degrees, and a total of four are mounted in FIG. Only the recording system of one of the magnetic heads to be used is shown.
[0019]
In the figure, reference numeral 1 denotes a divide-by-5 clock from an input clock, and outputs a divide-by-5 circuit. Reference numeral 2 denotes a head switch pulse generated based on a pulse synchronized with the rotation phase of a rotating drum (not shown). This is a data processing unit that receives recording data and performs processing such as 24-25 conversion on the basis of the divided-by-5 clock from the divided-by-5 circuit. Reference numeral 3 denotes a parallel-serial conversion unit that receives the recording data that has been processed by the data processing unit 2 in parallel and serially outputs it based on a clock.
[0020]
A head switch pulse generated based on a pulse synchronized with the rotation phase of the rotating drum, a clock, and a divided-by-5 clock from the divided-by-5 circuit are input to determine a delay correction amount in the delay correcting circuit 5. This is a delay correction amount determination circuit that outputs this to the delay correction circuit 5.
[0021]
Reference numeral 5 denotes the recording data output from the parallel-serial converter 3, the delay correction amount information and the clock from the delay correction amount determination circuit 4, and the delay correction amount information from the delay correction amount determination circuit 4. This is a delay correction circuit that delays recording data and outputs it to a magnetic head.
[0022]
FIG. 2 is a diagram for explaining the operations in the delay correction amount determination circuit 4 and the delay correction circuit 5. FIG. 2A shows a divide-by-5 circuit 1, a parallel-serial converter 3, a delay correction amount determination circuit. 4, clocks input to the delay correction circuit 5, FIG. 5B shows a divide-by-5 clock output from the divide-by-5 circuit 1, and FIG. 6D shows the data processing unit 2 and the correction amount determination circuit 4. The head switch pulse input to each is shown.
[0023]
FIG. 5C shows the operation of the internal counter of the delay correction amount determination circuit 4, which is incremented at the timing of the input clock with 0 as the initial value, and is initialized at the falling edge of the divided by 5 clock. Reset to zero.
[0024]
Then, the delay correction amount determination circuit 4 internally generates an edge detection signal of the head switch pulse as shown in FIG. 5E, which becomes H at the rising timing of the clock next to the timing at which the head switch pulse is switched, and then The count value of the counter is output to the delay correction circuit 5 as delay correction amount information at the rising timing of the clock.
[0025]
In the example shown in FIG. 2, the edge detection signal of the head switch pulse becomes H when the count value of the counter is 1, and the delay correction amount determination circuit 4 outputs the count value of 2 to the delay correction circuit 5 as delay correction amount information. is doing. Then, the delay correction circuit 5 delays the output from the parallel-serial conversion unit 3 by 2 clocks as shown in FIG.
[0026]
In the conventional digital signal recording apparatus, for example, even when the head switch pulse shown in FIG. 4D is slightly changed, the output of the parallel-serial conversion unit 3 for recording on the magnetic tape is the timing of the divide-by-5 clock which is unrelated to this. Therefore, the time from the switching timing of the head switch pulse to the start timing of signal recording cannot be made constant.
[0027]
On the other hand, in the digital signal recording apparatus according to the present invention, since a delay amount corresponding to the timing of the head switch pulse is added to the output of the parallel-serial conversion unit 3 and this is recorded on the magnetic tape, The time from the switching timing to the start timing of signal recording can be made substantially constant.
[0028]
That is, the delay correction amount determination circuit 4 determines the delay correction amount as 2 when the counter value is 0 at the timing when the head switch pulse is input, and sets the delay correction amount when the counter value is 1. 3. When the counter value is 2, the delay correction amount is 4; when the counter value is 3, the delay correction amount is 0; when the counter value is 4, the delay correction amount is 1. The time from the switching timing of the head switch pulse to the timing of signal recording can be made substantially constant.
[0029]
FIG. 3 is a diagram showing an example of the configuration of the delay correction circuit 5. Reference numerals 5a to 5d denote shift registers that output the input serial data constituting recording data by delaying the input clock by one clock, and 5e is a parallel serial. The selector 3 switches the serial data from the conversion unit 3 and the outputs of the shift registers 5a to 5d from the delay correction amount determination circuit 4 based on the delay correction amount information.
[0030]
In the above configuration, when the delay correction amount from the delay correction amount determination circuit 4 is 0, the serial data from the parallel-serial conversion unit 3 is selectively output and the delay correction amount is 1. When the serial data from the shift register 5a is selectively output and the delay correction amount is 2, the serial data from the shift register 5b is selectively output and when the delay correction amount is 3, the shift register 5a When the serial data from 5c is selectively output and the delay correction amount is 4, the serial data from the shift register 5d is selectively output.
[0031]
As described above, in the digital signal recording apparatus according to the present embodiment, four magnetic heads are mounted on the rotating drum. In each recording system, the time from the switching timing of the head switch pulse to the start timing of signal recording is set. Since it can be almost constant, the time from the start timing of signal recording by the + azimuth head to the start timing of signal recording by the azimuth head between the azimuth head and the − azimuth head forming the pair head is made almost constant. can do.
[0032]
Even when four magnetic heads are mounted on the rotating drum and there are four recording systems shown in FIG. 1, the clock shown in FIG. 2 (a) and 5 shown in FIG. 2 (b) are provided. The divided clock is shared by each recording system. In addition, the head switch pulse of the + azimuth head and the −azimuth head is generated from the pulse synchronized with the rotation phase, but is synchronized with the rotation phase between the magnetic heads of the same azimuth that are provided on the rotating drum so as to face each other at approximately 180 degrees. The timing from the pulse timing to the switching timing of the head switch pulse is set to a fixed time, and between the magnetic heads of different azimuths provided adjacently on the rotating drum, the timing of the head switch pulse is determined from the timing of the pulse synchronized with the rotational phase. Different times are set up to the switching timing as shown in FIG.
[0033]
As described above, in the digital signal recording apparatus according to the present invention, the time from the switching timing of the head switch pulse to the start timing of signal recording even when the divided clock is used as the processing of the recording data in the data processing unit 2. In particular, when processing such as 24-25 conversion that is often used in a digital signal recording system is performed, the accuracy of the error can be suppressed within the range of one clock instead of the range of the divided clock by one. It is effective.
[0034]
In addition, the digital signal recording apparatus according to the present invention is not only used in the case of using a divide-by-five clock such as 24-25 conversion, but also in a recording apparatus using another divided clock having a pulse interval larger than the recording clock. Needless to say, it can be applied.
[0035]
【The invention's effect】
According to the digital signal recording apparatus of the present invention, the first and second tracks are simultaneously formed by using the first and second magnetic heads having different azimuths provided adjacent to each other on the rotating drum, and digital data is formed. Can be set to a substantially constant time from the recording start timing by the first magnetic head to the recording start timing by the second magnetic head, so that the reproduction of the reference signal in the first and second tracks is performed. There is an effect that accurate tracking control can be performed by a reproducing apparatus that performs track control based on the timing difference.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a digital signal recording apparatus according to the present invention.
FIG. 2 is a diagram for explaining operations of a delay correction amount determination circuit and a delay correction circuit;
FIG. 3 is a diagram illustrating an example of a configuration of a delay correction circuit.
FIG. 4 is a diagram for explaining the principle of tracking control based on a difference in reproduction timing of a reference signal.
FIG. 5 is a diagram illustrating an example in the case where there is a deviation in the track formation timing of adjacent tracks.
FIG. 6 is a diagram for explaining a conventional digital signal recording apparatus.
FIG. 7 is a diagram for explaining fluctuations in signal recording start timing.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... 5 frequency dividing circuit 2 ... Data processing part 3 ... Parallel serial conversion part 4 ... Delay correction amount determination circuit 5 ... Delay correction circuit 5a thru | or 5d ... Shift register 5e ... Selector

Claims (2)

A digital signal recording apparatus for recording digital data while simultaneously forming first and second inclined tracks on a magnetic tape using first and second magnetic heads arranged adjacent to each other on a rotating drum. ,
N-divided clock output means for generating an n-divided clock that is n-divided (n is an integer of 2 or more) from a recording clock for recording the digital data;
A pulse synchronized with the rotation phase of the rotating drum, recording data, and an n-divided clock from the n-divided clock output means are input, and the recording data is signal-processed with the n-divided clock and output. Data processing means;
A pulse synchronized with the rotation phase of the rotating drum and the n-divided clock are input, and a delay amount corresponding to the timing difference between the input timing of the pulse and the switching timing of the n-divided clock is determined and output. A delay amount determining means;
Respectively provided a recording system circuit Ru and a delay means for applying a delay corresponding to the delay amount determined by the delay determining means to the recording data to said first and second magnetic heads,
The recording clock and the n-divided clock are shared by the recording system circuits of the first and second magnetic heads,
The first and second magnetic heads use the first and second magnetic heads so that the recording data output from the delay means of the respective recording system circuits have different azimuths on the first and second tracks. A digital signal recording apparatus for recording while simultaneously forming tracks.   The delay amount determining means includes a first time from a pulse timing synchronized with the rotational phase of the rotating drum to a recording start timing by the first magnetic head, and a pulse timing synchronized with the rotational phase of the rotating drum. And the second time from the second magnetic head to the recording start timing is determined so that the time corresponding to one clock of the recording clock becomes an error, and the delay amount is determined. The digital signal recording apparatus according to claim 1.

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