JPH1098397A - Interleaver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a large interleaving distance in a small scale circuit. SOLUTION: An interleaver consists of a first switch 11a for distributing input data to respective lines, plural lines 12 which are selected by the first switch 11a for storing data and executing delay for a prescribed time, a delay element 13 which is longitudinally connected to the respective lines 12 so as to obtain the desired delay time, the second switch 11b which are successively connected to the respective lines 12 ad synchronized with the first switch 11a so as to selectively execute an output and a exchanging part 1a for changing the arrayal of input data, which is provided in the preceding stage of the first switch 11a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleaver for continuously rearranging continuous transmission data.

[0002]

2. Description of the Related Art Conventionally, in order to reduce burst errors in a transmission line in satellite communication or the like, an interleaver has been used as an apparatus for rearranging continuous transmission data. By using an interleaver to rearrange the data in a discrete manner, it is possible to prevent the information to be successively from being damaged as a whole.

FIG. 4 is a block diagram of a main part of a conventional convolutional interleaver. It comprises a first switch 11a for distributing input data to each line, a plurality of lines 12 for storing data and delaying the required time, and a second switch 11b for sequentially connecting to each line 12 and selectively outputting. The continuous transmission data (bit stream) is supplied as input data to the first switch 11a on the input side of the convolutional interleaver.
The first switch 11a and the second switch 11b are connected to a terminal 1, a terminal 2,.
It operates so that each of the lines 12 may be sequentially selected and switched.
On the other hand, in each of the lines 12 except the first line, as shown in FIG. 4, a delay element 13 that sequentially increases so as to have a delay value s, 2s, 3s,. Cascaded. That is, the delay value of the delay element 13 connected to the g-th line is “g−1”.

[0004] The convolutional interleaver configured as described above performs an operation of rearranging data randomly. For example, g
Is 3, and the number of lines is 3, as shown in FIG.
When data “GFEDCBA” is input, the interleaver outputs discrete data “... JCEG0BD00A” as exemplified in “Interleaved data” in FIG. However, “0” is the initial value of the delay element 13. In general, a convolutional interleaver can increase an interleaving distance (distance between discretely rearranged data) by increasing the number of lines.

[0005] By the way, focusing on the interleaving distance, the larger the distance between the discretely rearranged data, the more advantageous it is against burst errors in the transmission path.

However, in order to increase the interleaving distance, the number of lines must be increased, in other words, the number of required delay elements increases. Therefore, an increase in the number of delay elements 13 provided for each line 12 is associated with an increase in the circuit scale, which causes a problem of an increase in cost.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an interleaver which can obtain a large interleaving distance with a small-scale circuit.

[0008]

In order to achieve the above object, a plurality of delay units for delaying input data by a predetermined delay time, and a synchronous selection operation provided on the input and output sides of the plurality of delay units. In the interleaver composed of two switch sections for performing the above, a rearrangement section for rearranging data is cascade-connected to the input side.

Further, the rearrangement section and the switch section are constituted by a counter, and a plurality of detection / control sections for detecting an output value of the counter and controlling writing / reading of the delay element.

Further, the delay element is constituted by a shift register.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS With the above configuration, the transmission data of the supplied bit stream is subjected to the first rearrangement (interleaving) by the rearrangement unit.
As shown in FIG. 5, the second interleaving by the conventional convolutional interleaver is performed, and a large interleaving distance is secured by rearrangement twice in total.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an interleaver according to the present invention will be described.
This will be described in detail with reference to the drawings. FIG. 1 is a main block diagram showing an embodiment of an interleaver according to the present invention. 11a is
This is a first switch for distributing input data to each line. Reference numeral 12 denotes a plurality of lines which are to be selected by the first switch 11a and which store data and delay the required time. 13
Is a delay element cascaded to each line 12 to obtain a required delay time. Reference numeral 11b denotes a second switch which is sequentially connected to each line 12 and selectively outputs in synchronization with the first switch 11a. Reference numeral 1a denotes a rearranging unit for rearranging input data provided at a stage preceding the first switch 11a.

The general operation of the interleaver according to the present invention will be described. The transmission data of the supplied bit stream is
The first sorting (interleaving) is performed in the sorting unit 1a. For example, [Original data]: JIHGF
EDCBA is rearranged by: JIHKFEG
It is converted to CBAD or the like, and further performs the same second interleaving as the conventional convolutional interleaver as shown in FIG.

FIG. 2 is a detailed block diagram showing an embodiment of an interleaver according to the present invention. 1 is an n-ary counter that counts clocks. Reference numeral 2 denotes a plurality of detection / control units which detect the output value of the n-ary counter 1 and perform data write control on the corresponding delay elements. For example, as shown in FIG. , "4 detection / control units", "1 detection / control unit",... Reference numeral 3 denotes a plurality of shift register units for delaying input data by a required delay time, the first shift unit having one storage cell,
The second shift unit has two cascade-connected memory cells, the third shift unit has three cascade-connected memory cells, and a shift register having cells that sequentially increase in number is arranged. The cascade connection is performed for each order of the control unit 2 and each output is connected to one output terminal.

The detailed operation of the interleaver according to the present invention will be described with reference to FIGS. FIG. 3 is a time chart for explaining the data rearrangement of the interleaver and the data delay operation by the shift register according to the present invention. First, after the initial reset, the n-ary counter 1 increments the count value every clock, and sets “0, 1, 2,..., N−
, 1, 0, 1, 2,... Are repeatedly output at a cycle of n clock times. In the first cycle after the counting operation of the n-ary counter 1 starts, the one that detects the count value “0” is “0 detection / detection” arranged at the head position of the detection / control unit 2.
As shown in FIG. 3, the “0 detection / control unit” supplies a write control signal to a “first shift unit” connected to the subsequent stage, and converts one of the input data of the bit stream into one. Control to write. At this time, data previously stored in the shift register is output. However, in the first cycle, the shift register is reset, for example, “0”
Value. Also, the one that detects the next count value “1” is the “1 detection / control unit” arranged at the third position, and the “0 detection / control unit” is, as shown in FIG. Control is performed so that input data is written to the “third shift unit”. At this time, data previously stored in the third storage cell constituting the shift register is output. However,
In the first cycle, the shift register is reset, for example, to a “0” value. Thereafter, the same operation is performed until the count value reaches “n−1”. Therefore, the transmission data of the supplied bit stream includes the “first shift unit” and the “third shift unit”.
, Etc., are rearranged and written in the corresponding shift register sections 3 according to the arrangement of the detection / control section 2.

In the second cycle, the "0 detection / control unit" detects the first count value "0" of this cycle, and
As shown in (1), the write control signal is supplied to the "first shift unit" to write new data, and the data stored in the shift register unit 3 is shifted in the first cycle and output with a delay of one cycle. What is necessary is that the “first shift unit” has one memory cell. "1 detection / control unit" has a count value of "1"
Is detected, new data is written to the "third shift unit", and the contents of the memory cells are shifted and output. Thereafter, the same operation is performed until the count value reaches “n−1”.

As described above, the transmission data of the supplied bit stream is rearranged and written in each shift register unit 3 (first rearrangement), and then the "first shift" is transmitted.
The unit outputs data with a delay of one cycle, and the second shift
The unit outputs data with a delay of two cycles, and the third shift
The unit performs data output with a delay of three cycles,..., Performs rearrangement of output data (second rearrangement) according to the difference in delay time. The second rearrangement operation is the same as the operation of the conventional convolutional interleaver shown in FIG. 4 (FIG. 5).

The shift register unit 3 is provided with, for example, a dual-port FI capable of independently accessing an input and an output.
It can be easily realized by using FO (First In First Out) or the like.

[0019]

As described above, the present invention provides an interleaver capable of obtaining a large interleaving distance with a small-scale circuit. Therefore, there is an advantage that an interleaver used to reduce a burst error in a transmission line in satellite communication or the like can be realized at low cost. In addition, since the rearrangement of a plurality of data is performed, the secrecy of the data can be improved.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of an interleaver according to the present invention.

FIG. 2 is a detailed block diagram showing an embodiment of an interleaver according to the present invention;

FIG. 3 is a time chart for explaining data rearrangement of an interleaver and a data delay operation by a shift register according to the present invention;

FIG. 4 is a main block diagram of a conventional convolutional interleaver.

FIG. 5 is a diagram for explaining an operation of rearranging data randomly by a convolutional interleaver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-ary counter 2 Detection / control part 3 Shift register part 1a Rearrangement part 11a First switch 11b Second switch 12 Line 13 Delay element

Claims (3)

[Claims] 1. An interleaver comprising: a plurality of delay units for delaying input data by a predetermined delay time; and two switch units provided on an input side and an output side of the plurality of delay units for performing a synchronous selection operation. An interleaver characterized in that a rearrangement unit for rearranging data is cascaded on the input side. 2. The device according to claim 1, wherein the rearrangement unit and the switch unit include a counter, and a plurality of detection / control units that detect an output value of the counter and perform write / read control to a corresponding delay element. The described interleaver. 3. The interleaver according to claim 1, wherein said delay element comprises a shift register.