JPS63131305A - Digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To reduce the discontinuity of edition points by separating data before and after the edition point into off/even number of samples and fading out the preceding sample and fading in the subsequent sample so as to attain the cross-fade processing. CONSTITUTION:A data frame 3-1 is recorded on a track 5 by positive azimuth on the final track of a preceding signal and a data frame 4-2 is recorded on a track 6 on a head track of a succeeding signal by a negative azimuth and the same frame address number is added to the tracks 5, 6. The data frame 3-2 for the preceding signal and the data frame 4-1 for the succeeding signal are deleted respectively and not recorded. Thus, the cross-fade processing between the preceding and succeeding signals is attained by the tracks 5, 6 of the frame number (i+2). Thus, the discontinuity at the edition point is switched smoothly and the listening sense of disorder in the said part is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital audio cheap recorder.
), regarding a digital audio tape recorder suitable for editing.

[Conventional technology]

Editing on conventional analog tape recorders is called hand-cut editing using tape splices, which is described on page 579 of Hi-Fi Tape Recorder (Radio Gijutsu Sha, published in 1972), and the tapes of both signals are cut diagonally. This had the effect of crossfading both signals, but digital audio tape recorders do not take similar processing into consideration, and an external editing machine It was supposed to be compatible.

On the other hand, in conventional rotary head type VTRs, when stopping the recording state, a predetermined The head stopped in this order, and the stop of recording by the recording head was not synchronized with the recording signal field.

[Problem that the invention seeks to solve]

Digital audio tape recorders do not take cross-fade processing into consideration, and there is a problem in that the sound becomes discontinuous at editing points.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal recording and reproducing apparatus that reduces the problem of discontinuities by performing cross-fade processing at discontinuities.

[Means for Solving the Problem] The above object is achieved by dividing the data at the editing point into nine odd and even samples.

[Effect]

The data before and after the editing point are separated into odd and even samples, the previous sample is faded out, and the subsequent sample is faded in.

This performs cross-fade processing and reduces discontinuities at editing points.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a circuit configuration diagram of a digital signal recording/reproducing apparatus for performing recording capable of cross-fade processing and/or for reproducing the recorded signal. First, the operation for recording will be explained.

During recording, an analog signal input from the input terminal 26 is converted into a PCM signal by the A/D converter 25. Note that the input signal may be a PCM signal output from another PCM signal reproducing device or a digital signal other than the PCM signal. In this case, the A/D converter 25 is unnecessary. This also applies to output. The PCM signal converted by the A/D converter 25 is written into the RAM 21 through the pass line 20. The write address of the RAM 21 at this time is generated by the input/output address generation circuit 17.

Incidentally, when writing the PCM signal to the RAM 21, the recording signal can be monitored from the output terminal 27 by simultaneously inputting it to the D/A converter 24 through the error correction circuit 23. At this time, the error correction circuit 26 may be controlled so as not to operate.

The PCM signal written in the RAM 21 is read out according to the address generated by the correction address generation circuit 16, and is input to the error correction circuit 22 through the pass line 20, where an error correction code is generated. That is, the error correction circuit 22 generates an error correction code during recording, and corrects errors in the reproduced signal using the error correction code during reproduction. In the error correction circuit 22, the input PC
An error correction code is generated based on the M signal, and the generated error correction code is written into the RAM 21.

After the error correction code is generated, the PCM signal and the error correction code stored in the RAM 21 are read out according to the address generated by the recording/reproduction address generation circuit 11, and then sent to the pass line 20 and the interface circuit 6.
The signal is input to the recording circuit 5 through. In the recording circuit 5, addition and modulation of synchronization signals, control signals, etc. are performed. After being amplified by the recording amplifier 4, the rotary head 2
is recorded on the magnetic tape 1 by. The rotating head 2 is composed of two heads A and B mounted on a cylinder. The magnetic tape 1 is wound around a cylinder, and the angle of the winding is usually 180 degrees or less, for example 90 degrees. Then, when the head comes over the magnetic tape, a signal is recorded.

The timing generation circuit 15 generates timing signals for controlling various parts using the clock oscillated by the oscillation circuit 14. The excavation frequency of the oscillation circuit 14 is selected to be an integral multiple of the sampling frequency of the PCM signal. The oscillation circuit 10 oscillates a clock having a frequency corresponding to the transmission rate of the recording signal. Then, PCM signals and error correction codes are sequentially recorded according to this clock. Switching circuit 18.
Reference numeral 19 is for switching the address of the RAM 21. Further, the servo circuit 13 controls the rotational phase of the rotary head 2. The position detection circuit 12 detects the phase of the cylinder based on a reference signal indicating the position of the cylinder. Then, the recording timing is determined according to this reference signal.

The switching circuit 3 is a head switching circuit, and outputs a recording signal to the rotary head 2 during recording, and outputs a reproduction signal from the head to the reproduction amplifier 7 during reproduction.

FIG. 2 shows the recording pattern on the magnetic chip 1.

30 indicates one track. In one track,
PCM signals and error correction codes are divided into a plurality of blocks, for example 128 blocks, and recorded. FIG. 3 shows the configuration of one block. 31 is a synchronization signal, 32 is P
A control signal related to the CM signal, 33 a block address indicating the block number, and 34 a PCM signal and an error correction code.

FIG. 4 shows the timing of inputting a PCM signal, generating an error correction code, and recording during recording.

35 is the writing timing from the A/D converter 25 to the RAM 21, 36 is the timing of generating the error correction code, 37
38 is a reference signal for the servo circuit 13, 38 is a position detection signal for the rotary head 2, 39 is a read timing from the RAM 21 to the recording circuit 5, and 40 is a recording timing on the magnetic tape. 35, 3, 6.39 The number in K is RAM21
It shows the storage area of . That is, the RAM 21 has a capacity to store four tracks of PCM signals and error correction codes, and has a first area, a second area, a third area, and a fourth area, respectively.

Further, A and B in 40 indicate recording heads. Writing from A/D converter 25 to RAM 21 is as follows:
This is done at a constant cycle depending on the sampling frequency.

For example, if the chimpling frequency of the PCM signal is 48KHz
If we record a 2-channel PCM signal,
It is necessary to write iC once for approximately 10 μsec.

Here, if the access frequency of the RAM 21 is 64 times the sampling frequency, that is, 5,072 times, and a PCM signal with a quantization bit count of 16 bits is written in units of 8 pits, the ratio of 2 out of 32 accesses is It is necessary to write with . Writing from the A/D converter 25 to the RAM 21 takes one rotation of the rotary head (560
°) to write to the first and second areas, and in the next rotation write to the third area.
and written to the fourth area. At this time, as shown at 36, error correction codes are generated for the PCM signals written in the first and second areas in the previous rotation. PCM written in the third and fourth areas! Regarding the code, an error correction code is similarly generated in the next rotation. After the error correction code is generated, the PCM signal and the error correction code are read out from the RAM 21 at timing 39 and recorded on the magnetic tape 1 at timing 40.

The recording timing is determined based on the position detection signal 38. The position detection signal 58 indicates the position of the rotary head 0 (the position where the head A starts scanning the magnetic tape 1). In the servo circuit 13, the timing generation circuit 15 detects the fall of the generated reference signal 37 and the position detection signal 3.
The rotational phase of the rotary gear 2 is controlled so that the rotation angles 8 and 8 coincide with each other. Then, the recording/reproduction address generation circuit 11 determines the recording timing based on the phase detection signal 38, and
21, PCM (No. 1 and error correction code) are successively output. This readout is performed at a frequency corresponding to the recording rate oscillated by the oscillation circuit 1°.

In the rotary head type digital audio tape standard, the tracking signal, ie, the ATF signal, is repeated in units of four tracks, as shown in the sixth factor.

First, the track is moved to the positive (or +) position of KA as shown in Figure 2.
) azimuth tracks and B negative (or -) azimuth tracks are recorded alternately. Further, the identification signal of the PCM signal area includes a frame address, and in this frame, adjacent positive and negative azimuth tracks are bare and the same frame address number is added. This frame address is composed of 4 bits, and is recorded by repeating a bit pattern from 'oooo' to '1111', that is, from 0 to 15. Here, the tracking signal is recorded from repeated traps of a total of four tracks, two tracks with even frame address numbers and two tracks with odd frame address numbers. For example, the tracking signals for the A (positive azimuth) track at frame address 4 and the A (positive azimuth) track at frame address 6 have the same configuration.

For this reason, in order to continue recording the tracking signal from the recording end portion of the tape that has already been recorded, it is necessary to record the track azimuths alternately so that the tracking signals are continuous. For example, A with an even frame address
After the track, it is sufficient to record the signal of the B track with an even frame address.

Therefore, when recording later, the frame address number and A of the track immediately before and after recording.

Identify one of the B trunks, set the frame address to the same frame address number or the next number, and record it with a reverse asymmetrical head.

As described above (if you want to stop recording in the middle of a tape in consideration of the next continuous recording, or if you want to continue recording on the previous tape, you can re-record during playback by performing the above operations. It is possible to prevent or reduce the occurrence of abnormal sounds due to synchronization deviations, data discontinuities, etc. that occur at the joints or editing points.

Next, the operation when recording is stopped in the PCM signal recording/reproducing apparatus shown in FIG. 1 will be explained.

A signal from the recording stop signal input terminal 54 is input to the timing generation circuit 15. Based on the stop signal, the timing generation circuit 15 stops recording after the recording of the track with a predetermined field address number of the +azimuth track is completed, and outputs a stop control signal from the stop signal output terminal 55.

That is, the track A in Figure 2 and the track 40 in Figure 4.
It stops after 39 1 or 3 corresponding to 39 people are recorded.

Next, the operation of continuously recording on a prerecorded tape in the PCM signal recording/reproducing apparatus shown in FIG. 1 will be described.

The last track of recorded silver data is detected from the identification signal or the reproduction signal, and signals corresponding to the subsequent recording azimuth and frame address are recorded from the recording azimuth and frame address of the final track.

The recording system Kl records a track at a predetermined frame address with a positive azimuth head based on a recording stop signal, and then performs a stop process.

Here, the predetermined frame address is, for example, either or both of the case where the frame address is an odd number or an even number. That is, the data has a 1-track complete code structure with 2-track complete interleaving as shown in FIG. 7, and the tracking signal (ATP) has a 4-track complete code structure as shown in FIG.
It is completed with a track. Therefore, for example, if it ends at an even frame address (5), the next track will be β
) Tracking control during playback can be performed smoothly by recording from an even frame address.

As described above, in the recording system, it is possible to identify whether the last track of the already recorded signal or the track immediately before the track to be recorded is a track with a positive azimuth or a track with a negative azimuth, and the track number to be recorded. Record in track format.

This enables continuous playback between editing points during playback, including the tracking control signal.

Recording capable of cross-feed processing will be explained in more detail using the time charts and track patterns shown in FIGS. 8 and 9.

FIG. 8+a) shows a pre-signal period and a post-signal period, in which each rain period is divided into predetermined periods, for example 3oIT4S. The signals of each period are each divided into two booter frames and subjected to formatting processing including encoding processing. Each data frame is recorded on a track.

For example, the signals of period 2 of the previous signal are 2-1 and 2-
It is composed of two data frames of 2 and 2-1 is ct)
2-2 is recorded on the track ①, and 2-2 is recorded on the track ①. Here, the same track is recorded as in the track pattern shown in FIG. Here, b in (e) indicates the frame address number in the identification signal. Here, in the last track of the front signal, the data frame 3-1 is recorded on track ■ with a positive azimuth, and on the first track of the rear signal, the data frame 4-2 is recorded on the trunk ■ with a negative azimuth. The same frame address is added to ■ and ■.

In this way, data frames 3-2 of the previous signal and 4-1 of the subsequent signal are respectively deleted and not recorded. By this, L
+2 frame number track ■.

■ allows cross-fade processing between the front and rear signals.

Next, the frame address number and azimuth control operation will be explained in more detail using diagram 7110. In the timing generation circuit 15, only the portions related to this operation are described.

The extraction signal from the identification code extraction circuit 50 is input to the timing generation circuit 15. The frame address extraction circuit 10-1 extracts a frame address from the identification signal, and the extracted signal is used as the frame address signal generation circuit 10-1.
2, the frame address signal is generated, and is supplied to an identification signal generation circuit (not shown in the figure).

The azimuth control signal generation circuit 10-3 identifies the azimuth of the previous track, generates a signal for controlling the recording track azimuth based on the azimuth, and supplies it to the azimuth control circuit, although it is not shown in the figure. .

If the last recording track of the previous signal is a negative azimuth track, cross-fade processing cannot be performed, but it is necessary to identify whether the frame address is odd or even. By using a frame address and recording from the positive azimuth track, tracking control is less likely to be disturbed. Furthermore, cross-fade processing can be performed by overriding the signal to be recorded on the negative azimuth track of the subsequent signal on the negative azimuth track that is the final recording track.

Here, by additionally recording an identification signal on the last track during recording and the first track during re-recording, editing points can be extracted from the same identification signal during reproduction and cross-fade processing can be performed. This identification signal is recorded, for example, in the identification signal area of the PCM block.

Next, the case where reproduction is performed in the PCM signal recording and reproducing apparatus shown in FIG. 1 will be explained.

During playback, the switching circuit 3 is switched to the playback side by the recording/playback switching signal inputted from the input terminal 28, and the playback signal played back by the rotary head 2 is amplified and shaped and equalized by the playback amplifier 7. The signal is input to the reproduction circuit 8. The recording/reproduction switching signal also switches the operation timing of the RAM 21, switches the operation of the error correction circuit 22, and inhibits the operation of the A/D converter 25.

The reproducing circuit 8 demodulates the PCM signal and error correction code, and detects synchronization signals and control signals.

The PCM signal and error correction code demodulated by the reproduction circuit 8 are written into the RAM 21 via the interface circuit 9 and the pass line 20. The address of the RAM 21 at the time of writing is generated by the recording/reproduction address generation circuit 11 based on the block address in the synchronization signal and control signal detected by the reproduction circuit 8.

The PCM signal and error correction code written in the RAM 21 are read out according to the address generated by the correction address generation circuit 16, and are read out from the error correction circuit 2 through the path line 20.
2 and error correction is performed. error correction circuit 2
The PCM signal corrected in step 2 is written into the RAM 21 again.

The error-corrected PCM signal is sent to the RAM 21 according to the address generated by the input/output address generation circuit 17.
is read out from the error correction circuit 2 through the pass line 20.
3 is input. For errors that could not be corrected by the error correction circuit 23, error correction such as average value interpolation is performed to replace the error with the average value of the preceding and succeeding values, and the result is output to the D/A converter 24. Then, the D/A converter 24 converts it into an analog signal and outputs it from the output terminal 27. Note that the reproduced PCM signal is sent directly to the pond's PCM without converting it to an analog signal.
It may also be output to a device.

Address generation in the recording/reproduction address generation circuit 11, correction address generation circuit 16, and input/output address generation circuit 17 is the same during recording and reproduction because the address generated during recording and the address generated during reproduction are the same. Circuits can be shared.

FIG. 5 shows the timing of signal reproduction, error correction, and output of the PCM signal during reproduction. 70 is the reproduction timing from the magnetic tape 1, and 71 is the RAM from the reproduction circuit 8.
21 is a write timing, 72 is an error correction timing, and 73 is a read timing from the RAM 21 to the error correction circuit 23. Reproduction of signals from the magnetic tape 1 is performed in synchronization with the reference signal 37. Then, at timing 71, data is sequentially written into the first to fourth areas of the RAM 21. Error correction is performed on the reproduced signal written in the RAM 21 at timing 72. Note that although the timings of writing the reproduced signal and error correction partially overlap, there is no problem as long as the reproduction order and the error correction order are matched.

The error-corrected PCM signal is output at the next rotation (360°) of the rotary head.

The switching timing of the switching circuits 18 and 19 may be the same as that during recording.

In the timing diagram of FIG. 5, playback signal timing 7
0, and if A corresponding to write timing 7101 is the previous signal and B corresponding to write timing 2 is the subsequent signal, then in the area O and d of timing 73 when both signals are output, it corresponds to signal 1. A cross-fade process is performed in which the sample is faded out and the sample that overlaps with signal 2 is faded in.

The cross-fade process during playback will be described in detail below.

During playback, the identification code extraction circuit 50 detects the edit point data frame and generates a cross-fade processed signal. This cross-fade processed signal is used to perform fade-out processing of the previous signal and fade-in processing of the subsequent signal.

First, a rotating head type digital audio tape (R, -
DAT) So, for example, No. 1! In the case of a sampling frequency of 48 KHz and a 16-bit straight line on the quantum north side, which is called the mode of
It is divided into chimple groups for each aS. Here, the sample group is 288 in total, 144° samples each for Lch and Rch.
Consists of 0 samples. Here, the samples of each group are numbered from 0 to 1439 in the order of the signals. That is, Lo, L2. =-Llasa and Re, R2--&
a is is an even-numbered f-number, L+, Ls,
---Least and R+, FLs--R11as*
C indicates odd-numbered samples. Here Lc & and f4
．． c The even and odd samples of JL are divided,
The tape is formatted in a predetermined arrangement, and the PCM signal area on the tape is recorded by a + or - azimuth head.

FIG. 11 shows a recording method that allows cross-fade processing. For example, if a signal has already been recorded up to the middle of the tape and you want to continue recording another signal from the next track, the already recorded signal will immediately be recorded at +azimuth of the previous signal. Next, another signal, that is, a signal to be recorded one azimuth of the subsequent signal is recorded first. In this case, the signal to be recorded in +azimuth is deleted.

By doing this, half of the samples of the previous signal and half of the samples of the next signal are included between 3088 intervals. That is, the even-numbered samples of L6J and the odd-numbered samples of R6J of the previous signal, the even-numbered samples of RcZ of the subsequent signal, and the odd-numbered chimples of L6JL. In other words, both the front and rear signals are mixed equally.

FIG. 12 shows such distribution using analog signal sample points. cL) is the previous signal, b) is the subsequent signal, C) is the overlap of both signals, d) is the waveform diagram when cross-fade processing is performed, ○, Δ are data, . . . , M are lost data It is.

Next, the cross-fade process will be explained in more detail.

In the rotating head type digital audio team '17, Mode! , I[, the L channel signal fades out the even numbered samples and fades in the odd numbered chimples, and the R channel signal fades out the odd numbered samples and fades out the even numbered samples. Fade in the sample.

In this way, by fading out the signal of the positive azimuth track and fading in the number of the negative azimuth track, it is possible to cross-fade the front signal and the rear signal.

The cross-fade process will now be explained in more detail with reference to FIG. 15.

The samples of the front signal (a) and the rear signal (b) are divided into two, for example, between the cross-fade areas 5ashs.

Here, by fading the front signal (α) as shown by the broken line and adding the rear signal (b) while fading in as shown by the broken line, a signal like (C) is obtained, and the unlucky α portion becomes gentle. Here, signals (e) and (j9 are examples of cross-fade control signals, and (e) is temporarily decreased, (
0 indicates a curve that increases temporarily.

Next, the cross-fade processing circuit 51 will be explained. Regarding the data at the edit point recorded in the memory 21, the positive azimuth track data is read out, a process is performed to attenuate the temporary value within the track data, and the same area of the memory 21 is looked at again.

Next, the negative azimuth track data is read out, similarly processed to increase the temporary value, and written in the same area of the memo 921 again.

Similar processing can alternatively be performed before, after, or within the error correction circuit, before, after, or within the digital filter 52, or in the digital-to-analog converter 24.

In other words, cross-fade processing involves a method in which the data in the RAM 21 is read out once, arithmetic processing equivalent to cross-fade is performed, and then recorded in the RAM 21 again. There are a method in which the signal is supplied to the D/A after performing arithmetic processing corresponding to a fade, a method in which cross-fade processing is performed using a digital filter, and a method in which cross-fade processing is performed using the D/A converter 24.

Next, cross-fade processing will be explained using a more specific example.

FIG. 14 is a block diagram of a specific embodiment of the cross-fade processing circuit. For example, the audio sample 14-1 is 16
A cross-fade processing circuit 14-3 performs predetermined attenuation processing corresponding to fade-in and fade-act to obtain a processing result 14-2.

This processing is carried out in the multiplication circuit 14-9 by the voice chimple 14.
This is done by multiplying -1 by the generated output of the multiplier generating circuit 14-8. The multiplication is controlled by the cross-fade processing signal 14-6, and the multiplier is set to 1 in areas other than the cross-fade area. Here, the multiplier generating circuit 14-8 is the counting circuit 14-7.
Generate based on the output of The counting circuit 14-7 counts the reset signal 14-5 of the data frame period and the clock 14-4 of the audio sample period.

The operations of the counting circuit 14-7 and the multiplier generating circuit 14-8 will be explained with reference to the timing chart of FIG. 15. This will be explained below with reference to FIG. Figure a) is audio sample 14-1.
shows the output timing. b) is the reset signal 14-5
will be output at the beginning of the crossfade area.

C) is the audio number A/14-IK synchronized pulse, d
) is reset by the reset signal 14-5, and the pulse C
) is the output of a counting circuit that counts For example, e) is a signal that is reset by the reset signal 14-5 and obtained by counting the rising edge of the 2° output in the counting circuit. -2
Generate a signal from the signal and e). Here e) 1
During the period 00, fade-in control is performed, and during the period 00, fade-act control is performed. t) is a signal indicating a cross-fade area, and a period of 1 indicates the cross-fade area.

Here, as the output of the multiplier generation circuit 14-8, for example, d
) 2.2 to 2 can be linearly increased or attenuated by controlling the polarity using e) and outputting it. That is, when e) is 0, the polarity is reversed, and when e) is 1, it is positive polarity.

In another embodiment, the multiplier generating circuit 14-8 may be a ROM or a PLA that is addressed by the output of the counting circuit 14-7.
A damping or increasing characteristic can be obtained depending on the value of .

An example of the above control is shown in FIG. This will be explained below with reference to FIG. 4) shows the output timing of the audio sample 14-1 as in FIG. 15a), FIG. 16b) shows the multiplier of each standardized sample, and C) shows the linear increase/decrease line.

A loss fade processing circuit as shown at 14-3 in FIG. 14 can be provided before the error correction circuit 23, digital filter 52, or D/A converter 24 in FIG.

〔Effect of the invention〕

According to the present invention, two signals, a signal composed of even samples and an independent signal composed of odd chimples, can be overlapped during a predetermined period of an editing point between two different signals. Further, by temporarily decreasing one value and increasing the other value, it is possible to smoothly switch back to the discontinuity at the editing point, which has the effect of reducing the audible discomfort at the same portion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the PCM signal recording and reproducing apparatus of the present invention, FIG. 2 is a recording pattern diagram on a magnetic tape, and FIG.
The figure is a block diagram, and Figure 4 is a timing diagram during recording.
Figure 5 is a timing diagram during playback, Figure 6 is a tracking signal format diagram, Figure 7 is an interleave format diagram, Figure 8 is a track configuration diagram, Figure 9 is a track pattern diagram on the tape, and Figure 10 is a diagram of the track pattern on the tape. Crossfade control circuit diagram, Figure 11 is an interseep format diagram on tape, Figure 12 is a crossfade waveform diagram, Figure 13 is a fade-in/fade act waveform diagram, and Figure 14 is an example of a crossfade processing circuit. FIG. 15 is a cross-fade processing timing chart, and FIG. 16 is a cross-fade control waveform diagram. 2...Rotating head, 3...Switching circuit, 4...
-Recording amplifier, 7...Reproduction amplifier, 5...Recording circuit, 6.9...Interface circuit, 8...Reproduction circuit, 10.14...Oscillation circuit, 11...Recording and reproduction address Generation circuit, 15... Timing generation circuit, 16... Correction address generation circuit, 17... Input/output address generation circuit, -18, 19... Switching circuit, 21-RAM22
...Error correction circuit, 23...Error correction circuit, 2
4...D/A converter, 25...A/D converter.・Decoy, ″, 1- 2nd mouth! Man La Encircle: 3/ , 52-13 5d/20 (Otoko Gen N \ Departure / 4 Kunio 75 Figure 'j)

Claims (1)

[Claims] 1. A digital signal processing circuit that performs predetermined processing on a digital signal to generate a recording signal during recording, and generates and outputs a digital signal from a reproduced signal during playback; a recording amplifier that amplifies the playback signal, a playback amplifier that amplifies the playback signal and equalizes its waveform and inputs it to the digital signal processing circuit, a head that records or plays back on the recording medium, and a head that outputs the output of the recording amplifier during recording. and a switching circuit that inputs the signal reproduced from the head to the reproduction amplifier during playback.
A digital signal recording and reproducing apparatus characterized in that the last track at the end of recording is a positive azimuth track in the CM signal recording and reproducing apparatus. 2. In the digital signal recording and reproducing apparatus according to claim 1, there is provided a recording azimuth detection circuit for the last track of the already recorded signal, a frame number extraction circuit, and a recording azimuth control circuit that receives the recording azimuth detection output as input. and,
The present invention is characterized in that it is equipped with a frame number control circuit that receives a frame number extraction output as an input, and starts recording at a frame number consecutive to the frame number of the final track using an azimuth head different from the azimuth of the final track. A digital signal recording and reproducing device.