JPS63130230U - - Google Patents
Info
- Publication number
- JPS63130230U JPS63130230U JP2347187U JP2347187U JPS63130230U JP S63130230 U JPS63130230 U JP S63130230U JP 2347187 U JP2347187 U JP 2347187U JP 2347187 U JP2347187 U JP 2347187U JP S63130230 U JPS63130230 U JP S63130230U
- Authority
- JP
- Japan
- Prior art keywords
- board
- latch
- selection address
- address decoder
- designate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009429 electrical wiring Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Inking, Control Or Cleaning Of Printing Machines (AREA)
- Control By Computers (AREA)
Description
第１図は枚葉輪転印刷機の電気装置末端部を示
す略図、第２図は本考案実施例の配線略図、第３
図は第２図の一部詳細図である。
Fig. 1 is a schematic diagram showing the end of the electrical equipment of a sheet-fed rotary printing press, Fig. 2 is a schematic diagram of the wiring of the embodiment of the present invention, and Fig. 3
The figure is a partially detailed view of FIG. 2.
Claims (1)
外部入出力データ配線を、複数本一組として夫々
ラツチ（一時記憶素子）ａを径てまとめて基板よ
り導出し、各組の配線を夫々並列に接続して一組
のデータバスラインとしてマイクロコンピユータ
ーに連結すると共に、マイクロコンピユーターか
ら複数本の基板選択用アドレス線ｆとラツチ選択
用アドレス線ｄを導出し、基板選択用アドレス線
ｆは基板アドレスデコーダｅに接続して複数個の
基板から一枚の基板を選択指定し、ラツチ選択用
アドレス線ｄは、前記基板アドレスデコーダｅに
導通するラツチアドレスデコーダｃに接続して、
各基板内において、前記複数個のラツチの中から
一個を選択指定する様構成され、コンピユーター
に接続する配線数を大巾に減少したことを特徴と
する簡単な電気配線を有する印刷機。 External input/output data wiring for switches, sensors, displays, etc. in each part of the printing machine is connected as a set of multiple wires, each connected through a latch (temporary memory element) a, and led out from the board, and the wires of each set are connected in parallel. They are connected to a microcomputer as a set of data bus lines, and a plurality of board selection address lines f and latch selection address lines d are led out from the microcomputer, and the board selection address line f is connected to a board address decoder. The latch selection address line d is connected to the latch address decoder c, which is electrically connected to the board address decoder e, to select and designate one board from a plurality of boards.
A printing machine having simple electrical wiring, characterized in that each board is configured to select and designate one of the plurality of latches, and the number of wirings connected to a computer is greatly reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2347187U JPS63130230U (en) | 1987-02-19 | 1987-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2347187U JPS63130230U (en) | 1987-02-19 | 1987-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63130230U true JPS63130230U (en) | 1988-08-25 |
Family
ID=30821800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2347187U Pending JPS63130230U (en) | 1987-02-19 | 1987-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63130230U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792994A (en) * | 1980-11-28 | 1982-06-09 | Nec Corp | Transmitting device |
| JPS6184251A (en) * | 1984-10-03 | 1986-04-28 | Tokyo Kikai Seisakusho:Kk | Preset system for rotary press |
-
1987
- 1987-02-19 JP JP2347187U patent/JPS63130230U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792994A (en) * | 1980-11-28 | 1982-06-09 | Nec Corp | Transmitting device |
| JPS6184251A (en) * | 1984-10-03 | 1986-04-28 | Tokyo Kikai Seisakusho:Kk | Preset system for rotary press |
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