JPS63129863U - - Google Patents
Info
- Publication number
- JPS63129863U JPS63129863U JP2347287U JP2347287U JPS63129863U JP S63129863 U JPS63129863 U JP S63129863U JP 2347287 U JP2347287 U JP 2347287U JP 2347287 U JP2347287 U JP 2347287U JP S63129863 U JPS63129863 U JP S63129863U
- Authority
- JP
- Japan
- Prior art keywords
- delay line
- delay
- phased array
- array sonar
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000000605 extraction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 240000001973 Ficus microcarpa Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
Description
第1図は本考案の一実施例のブロツク図、第2
図は本考案の一実施例のソナーに用いられるデイ
レーラインの概略構成図、第3図はデイレーライ
ンの回路例、第4図はデイレーラインの他の回路
例、第5図は更に他の回路例、第6図は遅延時間
を可変とした可変デイレーラインの回路例、第7
図はCRデイレーラインを通常のデイレーライン
と組合せた使用例、第8図はデイレーラインの周
波数特性を示すグラフ、第9図は従来の梯子形L
Cデイレーラインの構成図である。
1……送波パルス発生器、21〜2N……デイ
レーライン、41〜4N……振動子エレメント、
6……デイレーライン、7……加算回路、8……
デイジタルスキヤンコンバータ、11……RC移
相回路、12,13,16……オペアンプ、14
……抵抗、15……コンデンサ、17,21……
1単位デイレーライン、18……NPNトランジ
スタ、19……PNPトランジスタ、20……バ
リアブルキヤパシタ、22……CRデイレーライ
ン、23……LCデイレーライン。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a schematic configuration diagram of a delay line used in a sonar according to an embodiment of the present invention, FIG. 3 is an example of a delay line circuit, FIG. 4 is an example of another delay line circuit, and FIG. 5 is a further example of a delay line circuit. Other circuit examples, Figure 6 is a circuit example of a variable delay line with variable delay time, Figure 7
The figure shows an example of the use of a CR delay line in combination with a normal delay line, Fig. 8 is a graph showing the frequency characteristics of the delay line, and Fig. 9 shows a conventional ladder-shaped L.
FIG. 3 is a configuration diagram of a C delay line. 1... Transmission pulse generator, 2 1 to 2N... Delay line, 4 1 to 4N... Vibrator element,
6...Delay line, 7...Addition circuit, 8...
Digital scan converter, 11...RC phase shift circuit, 12, 13, 16... Operational amplifier, 14
...Resistor, 15...Capacitor, 17,21...
1 unit delay line, 18...NPN transistor, 19...PNP transistor, 20...variable capacitor, 22...CR delay line, 23...LC delay line.
Claims (1)
ームを電子的に制御して媒体中に照射し、反射波
による受信信号をデイレーラインにより各振動子
エレメント毎に所定量の遅延をさせて整相加算す
るフエーズドアレイソナーにおいて、能動素子の
互いに逆位相の一対の出力端子と次段への信号取
出し点との間に抵抗とコンデンサをそれぞれ接続
した複数の単位デイレーラインの直列回路からな
る一方向性のCRデイレーラインを用いて、各振
動子エレメントの受信信号を遅延させ、整相加算
することを特徴とするフエーズドアレイソナー。 (2) 前記CRデイレーラインを構成する抵抗と
コンデンサの何れか一方又は双方を変化させた可
変遅延時間のデイレーラインをダイナミツクフオ
ーカス又は波源トラツキングに用いることを特徴
とする実用新案登録請求の範囲第1項記載のフエ
ーズドアレイソナー。[Claims for Utility Model Registration] (1) It has a plurality of transducer elements, and an ultrasonic beam is electronically controlled and irradiated into the medium, and the received signal from the reflected wave is sent to each transducer element by a delay line. In a phased array sonar that performs phasing and summation with a predetermined amount of delay each time, a plurality of resistors and capacitors are connected between a pair of output terminals of an active element with opposite phases and a signal extraction point to the next stage. A phased array sonar characterized in that the received signals of each transducer element are delayed and phased and summed using a unidirectional CR delay line consisting of a series circuit of unit delay lines. (2) A request for registration of a utility model characterized in that a delay line with a variable delay time in which one or both of the resistor and capacitor constituting the CR delay line is changed is used for dynamic focusing or wave source tracking. Phased array sonar according to item 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2347287U JPH0526997Y2 (en) | 1987-02-19 | 1987-02-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2347287U JPH0526997Y2 (en) | 1987-02-19 | 1987-02-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63129863U true JPS63129863U (en) | 1988-08-24 |
JPH0526997Y2 JPH0526997Y2 (en) | 1993-07-08 |
Family
ID=30821802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2347287U Expired - Lifetime JPH0526997Y2 (en) | 1987-02-19 | 1987-02-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0526997Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003093385A (en) * | 2001-07-31 | 2003-04-02 | Koninkl Philips Electronics Nv | Beam forming system using analog random access memory |
-
1987
- 1987-02-19 JP JP2347287U patent/JPH0526997Y2/ja not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003093385A (en) * | 2001-07-31 | 2003-04-02 | Koninkl Philips Electronics Nv | Beam forming system using analog random access memory |
JP4510360B2 (en) * | 2001-07-31 | 2010-07-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Beam shaping system using analog random access memory |
Also Published As
Publication number | Publication date |
---|---|
JPH0526997Y2 (en) | 1993-07-08 |
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