JPS63129739A - Compression and expansion buffer - Google Patents

Abstract

PURPOSE:To obtain a compressing/expanding buffer suitable for a speed variable type TDMA communication system by accessing a data memory based on a clock being the result of selective output of the frequency-division of the system clock of a common data transmission line. CONSTITUTION:An address counter 4 is operated based on a gound system clock and a data by one TDMA (time division multiple access) frame of a transmission data from a ground system data transmission line is written in the data memory. On the other hand, a selection circuit 9 selects a frequency division output whose frequency is fs/2, for example, among frequency division outputs of a frequency division circuit 8, an address counter 5 is operated based on the fs/2 clock and the transmission data is read from a data memory 3 at a time assigned in its own station in one TDMA frame. Thus, the data transmission speed of a burst signal sent to a common data transmission line is a 1/2 speed of the system clock. Moreover, the data transmission speed in the common data transmission line is brought into an optional speed by selecting properly the output of the frequency division circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a compression/expansion buffer that converts the data transmission rate between a terrestrial data transmission line (terrestrial line) and a common data transmission line (satellite line).

(Prior Art) As is well known, in the time division multiple access (TDMA) communication system adopted in satellite lines, TDMA frames are time-divided and assigned to each earth station, and each earth station transmits data from the ground line. This method controls the transmission signal of the own station, which is data, to fit within the allocated time and sends it to the satellite line.

The transmission signal from each earth station is an intermittent signal having a period equal to the TDMA frame, and this intermittent signal is called a burst signal.

In the conventional TDMA communication system, the data transmission rate on the satellite line is uniquely determined by the system clock and is unchangeable, so the conventional compression/expansion buffer has the same data transmission rate on the satellite line and the terrestrial line. The data transmission rate is configured to perform speed conversion.

(Problems to be Solved by the Invention) In recent years, in order to prevent line quality deterioration of satellite lines, the quality required for data to be transmitted at the earth station scale,
A TDMA communication system that can relatively freely change the data transmission speed according to the degree of rain attenuation is being considered. "Study of Variable Speed TDMA Communication System").

Then, since the conventional compression/expansion buffer has a fixed conversion rate, there is a problem that it cannot be used in a variable transmission rate TDMA system as shown above.

The present invention has been made in view of these problems, and its purpose is to improve transmission rate variable TDMA by making it possible to appropriately select the data transmission rate in a satellite line.
An object of the present invention is to provide a compression/decompression buffer that can be used in a communication system.

(Means for Solving the Problems) In order to achieve the above object, the compression/decompression buffer of the present invention has the following configuration.

That is, the compression/decompression buffer of the present invention operates based on the terrestrial clock; a first controller for writing the transmission data into the data memory and reading the reception data from the data memory;
an address counter; a frequency dividing circuit that divides the system clock; a selection circuit that selectively outputs one of the divided outputs of the frequency dividing circuit; and an operation based on the output of the selection circuit. reading the transmitted data from the data memory as a burst signal sent to the common data transmission path, and writing the received data, which is the burst signal sent to the common data transmission path, into the data memory. Second to do that
This is a compression/decompression buffer characterized by having an address counter and;

(Function) Next, the function of the compression/expansion buffer of the present invention configured as described above will be explained.

The data transmission speed of the common data transmission path of the TDMA communication system is determined by the system clock frequency f, taking into account rain attenuation, etc.
Assuming that the speed is, for example, 1/2 of s, the operation of the transmission system when sending the transmission data as a burst signal to the common data transmission path is as follows.

The first address counter operates based on the terrestrial clock, and the first address counter operates based on the terrestrial clock, and the IT
Write the DMA frame to the data memory.

On the other hand, the selection circuit selects the divided output whose frequency is f5/2 from among the divided outputs of the frequency dividing circuit, and selects the divided output whose frequency is f5/2.
Send the clock to the second address counter. The second address counter operates based on this fs/2 clock and reads the transmission data from the data memory at the time allocated to its own station within the ITDMA frame.As a result, the burst data is sent to the common data transmission path. The data transmission speed of the signal is 1/2 the speed of the system clock. The data transmission speed on the common data transmission path can be set to any speed by appropriately selecting the output of the frequency dividing circuit.

Note that when the burst signal on the common data transmission path is sent to the terrestrial data transmission path as received data, the burst signal has a speed of f s / 2, so the second address counter has a speed of f s / 2. The first address counter, which operates based on the clock and writes received data into the data memory, operates based on the terrestrial clock and reads the received data from the data memory.

As described above, according to the compression/expansion buffer of the present invention, the system clock of the common data transmission path is divided into a frequency dividing circuit and a selection circuit which selects and outputs one of the divided outputs of the frequency dividing circuit. is provided on the common data transmission path side, and the data memory is accessed based on this selectively outputted clock.If the frequency dividing circuit divides the frequency by N, for example, the maximum data transmission speed by the system clock is 1
It is possible to realize a burst signal with a data transmission rate of /N, and it is also possible to easily realize a burst signal with several types of data transmission rates up to 1/N with the same circuit configuration. Thus, according to the present invention, it is possible to provide a compression/expansion buffer suitable for a variable speed TDMA communication system.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure shows a compression/decompression buffer according to an embodiment of the present invention.

In FIG. 1, 1 is a terrestrial system data timing circuit, 2 is a burst signal timing circuit, 3 is a data memory, 4 is an address counter on the terrestrial side (first address counter), and 5 is a common transmission path (satellite 6 is a selector that selects either a write address or a read address and supplies it to the data memory 3; 7 is a system clock generator for the common data transmission path; Reference numeral 8 indicates a frequency dividing circuit that divides the frequency of the system clock, and 9 indicates a selection circuit that arbitrarily selects several types of clocks supplied from the frequency dividing circuit and supplies the clocks to the address counter 5.

In the above configuration, if the transmission speed of the common data transmission path (satellite line) is 1/2 of the system clock, then
The selection circuit 9 selects, from among the frequency-divided outputs of the frequency divider circuit 8, the output in which the system clock is frequency-divided by 1/2. Since the transmission speed of the common data transmission path may change even during operation of the system, the selection circuit 9 is configured to appropriately change the frequency-divided output to be selected accordingly.

The terrestrial clock supplied to the retiming circuit 1 and the address counter 4 is determined according to the data transmission speed on the terrestrial data transmission path.
performs waveform shaping processing, timing control, etc. based on this terrestrial clock.

The function of the retiming circuit 2 is similar, but it operates based on the system clock (frequency fs).

Now, in the transmission mode, the PCM signal, which is the transmission data from the terrestrial data transmission line, is supplied to the data memory 3 via the timing circuit 1, so the address counter 4 operates based on the terrestrial clock. , outputs a predetermined address signal to the selector 6. The selector 6 selects the output of the address counter 4 and supplies the address signal to the data memory 3 as a write address.

As a result, PCM signals for the ITDMA frame are stored in the data memory 3.

After the storage operation is completed, the selector 6 selects the output of the address counter 5 at the time allocated to its own station within the ITDMA frame, and provides it to the data memory 3 as a read address.

As a result, the transmission data is output from the data memory 3 in a burst form, and a burst signal is sent to the common data transmission path via the retiming circuit 2. The transmission speed of this burst signal is 1/2 of the system clock.

Next, in the reception mode, the transmission speed of the burst signal on the common data transmission path is 1/2 of the system clock. The selector 6 first selects the output of the address counter 5,
This is given to the data memory 3 as a write address. As a result, the burst signal addressed to the local station within the ITDMA frame is stored in the data memory 3. When this storage operation is completed, the selector 6 then selects the output of the address counter 4 and uses it as a read address from the data memory 3.
give to As a result, the ITDMA portion of received data is sent to the terrestrial data transmission path.

The above operations can be summarized as shown in FIG. Second
In the figure, (A) shows the relationship between the data (transmission data and reception data) on the terrestrial data transmission path and the output of the address counter 4 (write address and read address).

In addition, (B) in the same figure shows the data on the common data transmission path (
The relationship between the transmission burst signal and the reception burst signal) and the output (read address and write address) of the address counter 5 that operates with a clock of f S /2 of the system clock of frequency fs is shown.

(Effects of the Invention) As described in detail above, according to the compression/expansion buffer of the present invention, the system clock of the common data transmission path is divided by a frequency dividing circuit and one of the frequency divided outputs of the frequency dividing circuit. A selection circuit for selectively outputting the output is provided on the common data transmission path side, and the data memory is accessed based on the selectively outputted clock.If the frequency dividing circuit divides the frequency by N, for example, the system It is possible to realize a burst signal with a data transmission rate up to 1/N of the data transmission rate by a clock, and it is also easy to realize burst signals with several data transmission rates up to 1/N with the same circuit configuration. can. Thus, according to the invention, variable speed TDMA
This has the effect of providing a compression/expansion buffer suitable for communication systems.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a compression/expansion buffer according to an embodiment of the present invention, and FIG. 2 is an operation time chart when the system clock is divided into 1/2. 1... Retiming circuit, 2... Retiming circuit, 3... Data memory, 4
...Address counter, 5...Address counter, 6...Selector, 7...
...System clock generator, 8...Divider circuit, 9...Selection circuit.

Claims (1)

[Claims] a data memory for storing transmitted data from the terrestrial data transmission path and received data from the common data transmission path; operating based on a terrestrial clock;
a first address counter for writing the transmission data into the data memory and reading the reception data from the data memory; a frequency division circuit that divides a system clock; and a frequency division circuit for the frequency division circuit. a selection circuit that selectively outputs one frequency-divided output from among the outputs; a selection circuit that operates based on the output of the selection circuit, and that outputs the transmission data as a burst signal sent to the common data transmission path; a second address counter for reading from the memory and writing the received data, which is a burst signal sent to the common data transmission path, to the data memory; .