SU1631738A1 - Synchronizer - Google Patents

Abstract

The invention relates to telecommunications and can be used in phototelegraphic systems for transmitting signals from newspaper strips via artificial Earth satellites. The purpose of the invention is the expansion of functionality. The synchronization device contains a receiving regenerator 1, a memory block 2, a clock r-r 3, a block for selecting 4 phase pulses, a block for angular synchronization 5, a block for correcting 6 the recording frequency, and a block for selecting 7 of the phasing mode. The operation of the device is based on the use of features of the transmitted signal having a cyclic structure. Each cycle — one scan line — consists of 20,480 clock intervals. At the beginning of each cycle, a phasing pulse consisting of 648 currentless parcels is transmitted, during which the scanning beams of the transmitting and receiving phototelegraph apparatus operating synchronously return to the beginning of the line. The goal is achieved by providing a mode of rewriting the plesiochronous signals of newspaper strips. The apparatus is characterized by the execution of memory block 2, 1C. f-ly, 2 ill.

Description

The invention relates to telecommunications and can be used in phototelegraphic systems for transmitting signals from newspaper strips via artificial Earth satellites.

The aim of the invention is to extend the functionality by providing a mode of rewriting the plesiochronous signals of newspaper strips.

Fig. 1 is a block diagram of the synchronization device; Fig. 2 shows an embodiment of a memory unit with a correction unit.

The synchronization device contains a receiving regenerator 1, a memory block 2, a clock generator 3, a block for selecting 4 phase pulses (PI), a frame synchronization block 5, a recording frequency correction block 6, and a phase mode selection block 7, which includes a waiting multivibra ; the torus 8, the differentiating unit 7, the keys 10 and 11, and the selector 12 of the filling signal, and the composition of the memory unit 2

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The first, second, and output registers 13–15, the write counter 16, the RAM block 77, the storage unit 18, the first and second switches 19 and 20, the decoder 21, the counter 22, and the read counter 23.

The operation of the device is based on the use of features of the transmitted signal having a cyclic structure. Each cycle — one scan line — consists of 20,480 clock intervals. At the beginning of each cycle, a phasing pulse consisting of 648 currentless parcels is transmitted, during which the scanning beams of the transmitting and receiving photo-telegraphic devices operating synchronously return to the beginning of the line.

At the beginning of work, a sequence of phasing pulses is transmitted, against the background of continuous current dressings - the Pause mode. After filling the original newspaper strip into the transmitting apparatus and confirming readiness for work, a Starting signal is transmitted from the newspaper receiving workshop (through a separate service channel), which activates transmitting and receiving phototelegraph devices. For eight cycles with this command, the phasing pulses are filled with a clock sequence of 1024 (or 512) kHz — a fill signal.

But at the end of the Start signal, the intervals between the phasing pulses (already without filling) are occupied by the transmitted information obtained as a result of scanning the original newspaper strip. The transmission time of one newspaper page is about three minutes, followed by the Pause mode, which usually lasts at least one minute to refill the original newspaper page on the program and film on the receiving side.

The next band is transmitted in the sequence already described.

The essence of the principle of operation of the proposed device is that in the Pause mode, the memory block 2 is periodically phased under the received signal, and during band transmission from the moment of the Start command, the phasing is turned off.

The signal received from the terrestrial channel through the line input of the device enters the input of the receiving regenerator 1, which converts the linear quasi-turn signal into a unipolar signal with simultaneous extraction of a clock signal. These signals are sent to the signal and to the first clock inputs of memory 2 and the signal sendings are recorded in the storage cells of this block. Information is read from memory cells of memory 2 by a clock signal received at the second clock input of memory 2 from clock 3. The read signal from memory 2 is fed to the output of the device and then radiated to the receiver.

The selection unit of 4 phasing pulses produces at its output a response every time a combination appears in the signal received from the terrestrial channel, corresponding to the phasing pulse.

The frame alignment unit 5 selects periodically the next phasing pulse and establishes cyclic synchronism. In the frame synchronization mode, the output of the cyclic synchronization block 5 generates a local sequence of phasing pulses, which coincide in form and time with that received from the terrestrial communication channel, but not subject to interference. Under the action of a local sequence of phasing pulses, a signal is received through the Key 11 through the second input of the selector 12 of the fill signal 12, which is received only during the phasing pulses.

In the absence of a fill signal at the output of the fill signal selector 12, a constant logic level is produced, at which the waiting multivibrator 8 is braked and a local sequence of phase pulses passes through the output of the key 10, from the rising edges of which the differentiating unit 9 produces narrow control pulses that phase the memory block 2 once per cycle.

Reception of the signal The start of the filling signal selector 12 triggers the waiting multivibrator 8, the signal from the output of which locks the key 10 for the transmission time of the band

and the phasing of memory unit 2 is not performed during this time.

Due to the multiplicity of the number of memory cells and the duration of the transmission cycle P 20480 20N (or 40N), the maximum possible one-time extensions or shortenings of the signal cycle at the output of memory 2 do not exceed one clock interval. The frequency of changing the duration of the cycle depends on the current frequency divergence and, if its value is (GB is once per 50 cycles (lines)).

Such distortions, operating only in the Pause mode, do not cause phasing of the receiving phototelegraph apparatus and are not reflected in the quality of the transmitted signals, since during the transmission of the newspaper strip, the phaseouting of the memory unit 2 does not occur and the cycle shortenings do not occur.

A block of elastic memory 2 of relatively large capacity (1024 bits) required in this device can be performed on random-access memory circuits with separate write and read addresses. However, such schemes have a relatively small number of storage cells. Thus, a 564-IR11 type of chip allows storing 8 four-bit layers (32 bits). To obtain the required volume of the storage unit, 32 such chips are necessary.

The memory unit 2 operates as follows.

The signal received from the terrestrial channel and the accompanying clock sequence are fed to the corresponding inputs of the first register 13, in which this signal is converted into a parallel form (4-bit words) for later recording into a relatively small capacity operational memory 17. Recording address signals are generated by a counter 16. i

The clock sequence from the clock generator 3, coming through the second clock input, is fed to the input of the counter 23.

The output signals of bits from the third to the tenth counters 23 are address read signals from the storage unit 18. These signals are sent to the first inputs of the first

19, the switch 19. The output signal of the second bit of the counter 23 controls the operation of the first switch by operating mode write-read the storage unit 18 and starts the counter 22.

The output signals of all its bits are address information recording signals in the storage unit 18 and are fed to the corresponding second inputs of the first switch 19. The direct recording and reading of information in the storage unit 18

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performed by the output of the first bit of the first counter 12. The address read signals from the operational storage unit 17 are the output signals of the first three bits of the counter 22.

Due to the plesiochronous clock frequencies coming through the first and second clock inputs of the 2% memory block, the recording frequency must be corrected. For this purpose, in the correction block 6, the sign of the divergence of equal frequencies of the frequencies received in the counters 22 and 16 is determined.

Depending on the result obtained, once during the division cycle of the counter 22, its division factor is changed by i1. At the same time, one informational spruce read with a permanent address from

5, the operational storage unit 17 is copied to the second register by the front of the signal from the output of the last (eighth) bit of counter 29. At the same time, the information loss during correction

0, the division factor of counter 22 does not occur. Indeed, with an increase in the division ratio, the same word with the same address is recorded in the storage unit 18.

5 When reducing the division ratio, the word not recorded in the storage unit 18 is stored in the second register 14 and the decoder 21 controlling the second switch 20 connects this word to the output of switch 20. The control signal for the operation of switch 20 is generated once per division cycle counter 23 and corresponds to the selected fixed address. The sum signal from the output of the second switch 20 from the parallel form (4-bit words) is serialized by the output register 15 using an auxiliary

Claims (2)

1. A synchronization device containing a receiving regenerator, the signal output and the output of the clock frequency signal of which are connected to the corresponding inputs of the memory unit, to the other clock input of which the output of the clock generator is connected, as well as the recording frequency correction unit and the frame synchronization block, , in order to extend the functionality by providing rewriting mode for plesiochronous signals of newspaper strips, a phasing pulses extraction unit and a phasing mode selection unit are introduced The signal output of the receiving regenerator is connected to the corresponding inputs of the phasing pulses selection unit and the phasing mode selection unit, and the output of the clock frequency signal is connected to the corresponding inputs of the frame synchronization unit, the phasing pulses selection unit and the phasing mode selection unit, the output of which is through the frequency correction unit the recording is connected to the installation input of the memory unit, and the output of the phase-out selection unit through the cyclic synchronization unit is connected to the control input b Phase mode selection lock. 0 five 0 five 2. The device according to claim 1, characterized in that the memory unit contains the first register and a record counter connected at the first clock input, the outputs of which are connected to the information inputs of the storage unit and the second register through the memory unit, the outputs of which are connected through the first switch to the output register, to the control input of which and to the control input of the first switch, the corresponding outputs of the decoder are connected, the inputs of which are connected to the control inputs of the storage unit and the second switch The ora and with the readout counter outputs, the clock input of which is connected to the output register clock input and is the second clock input of the memory unit, the readout counter clock output is connected to the corresponding counter input, the outputs of which are connected to the readout memory input inputs, to the clock input the second register and the corresponding inputs of the second switch, the outputs of which are connected to the address inputs of the storage unit, the signal input of the first register being the signal input set The th input of the counter is the setup input of the memory block whose outputs are respectively the outputs of the output register, the counter and the clock output of the read counter. PSX tok. f grs-g oh oh. tch-g