JPS6312939U - - Google Patents
Info
- Publication number
- JPS6312939U JPS6312939U JP10655286U JP10655286U JPS6312939U JP S6312939 U JPS6312939 U JP S6312939U JP 10655286 U JP10655286 U JP 10655286U JP 10655286 U JP10655286 U JP 10655286U JP S6312939 U JPS6312939 U JP S6312939U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- oscillation
- output signal
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000009499 grossing Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例の構成図、第２図は
従来のスイツチング装置の構成図でさる。
１……制御入力端子、２……発振回路、３……
トランス、４ａ……整流回路、４ｂ……平滑回路
、５……ＦＥＴ、６……電源、７……負荷、８…
…増幅器。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional switching device. 1... Control input terminal, 2... Oscillation circuit, 3...
Transformer, 4a... Rectifier circuit, 4b... Smoothing circuit, 5... FET, 6... Power supply, 7... Load, 8...
…amplifier.
Claims (1)
振回路と、この発振回路の出力信号を二次側へ伝
達するトランスと、このトランスの二次側より得
られる出力信号を整流する整流回路と、この整流
回路の出力信号を平滑して前記ＦＥＴのゲート・
ソース間に与える平滑回路とを具備するスイツチ
ング装置。 (2) 発振回路は、シユミツトトリガゲート回路
により構成され、所定論理レベルの信号が与えら
れると、発振を開始することを特徴とする実用新
案登録請求の範囲第(1)項記載のスイツチング装
置。[Claims for Utility Model Registration] (1) An FET, an oscillation circuit that outputs a signal at a predetermined frequency, a transformer that transmits the output signal of this oscillation circuit to a secondary side, and a signal obtained from the secondary side of this transformer. A rectifier circuit that rectifies the output signal, and a rectifier circuit that smooths the output signal of the rectifier circuit and applies it to the gate of the FET.
A switching device comprising a smoothing circuit applied between sources. (2) The switching device according to claim 1, wherein the oscillation circuit is constituted by a Schmitt trigger gate circuit and starts oscillation when a signal of a predetermined logic level is applied. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10655286U JPS6312939U (en) | 1986-07-11 | 1986-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10655286U JPS6312939U (en) | 1986-07-11 | 1986-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6312939U true JPS6312939U (en) | 1988-01-28 |
Family
ID=30982019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10655286U Pending JPS6312939U (en) | 1986-07-11 | 1986-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6312939U (en) |
-
1986
- 1986-07-11 JP JP10655286U patent/JPS6312939U/ja active Pending