JPS63128814A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To prevent the saturation of an output transistor (TR) by connecting a diode between a constant current path of a level shift stage and collectors of a phase inverting TR and the output stage TR. CONSTITUTION:In a conversion circuit comprising an ECL input stage CS, a level shift stage LS, and an output stage OP, the diode D1 is connected between a collector of the phase inverting TRQ6' and a node n4 of a constant current path where TRs Q12', Q14' of the shift stage LS and a resistor R21' are connected in series. Thus, when the TRQ6' is turned on, the potential of a node ns is decreased by the collector resistor and the TRQ6' approaches the saturation, a current flows from the node n4 to the node ns through a diode D1. Then the potential of the node n4 is decreased, the base potential is decreased and the saturation of the TRQ6' is prevented. The collector of an output TRQ9 of the output stage OP is connected to the other constant current path via diodes D2, D3 to prevent the saturation. As a result, the delay in the output is avoided without using a Schottky type TR and the leading is made steep to prevent the occurrence of the oscillation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to a TTL level signal output circuit in a logic integrated circuit made of bipolar transistors. The present invention relates to a technique that is effective when used in a level conversion circuit that converts an ECL level signal to a TTL level signal and outputs the signal.

[Conventional Technique #I] As a circuit that converts the output (ECL level) of a logic circuit consisting of an ECL circuit, which operates faster than a TTL circuit, into a TTL level signal and outputs the signal.

For example, there is a circuit as shown in Figure 2 (Japanese Patent Application No. 60-2
No. 09963), this circuit receives the potential of one output node of a current switch circuit CS that receives an ECL level signal by an emitter follower circuit EF, and supplies it to a so-called phase split transistor Q6 via a level shift circuit LS. A totem pole type output stage OP is driven to output a TTL level signal.

In the level conversion circuit shown in Fig. 2, each of the transistors Q to Q is composed of a Schottky transistor, so that it saturates when the phase split transistor Q6 and the output transistor Q are turned on. Therefore, the rise of the output signal is as steep as the fall.

However, SBD (Schottky barrier) is involved in the process.
If you try to apply a level conversion circuit like the one shown in Figure 2 to a logic integrated circuit that does not have a process to form a diode (diode), you will have to add a new process to form an SBD. becomes complicated and increases costs. On the other hand, the level conversion circuit in Fig. 2 is
If it is configured with a normal NPN transistor without a phase difference, the phase split transistor Q6 and the low-side output transistor Q, which form two signals with a phase difference of 180 degrees, will be easily saturated and the output will rise slowly. There is an inconvenience that this happens.

Therefore, the applicant has proposed at least a phase split method.
We have developed a level conversion circuit as shown in Figure 3, which prevents the saturation of transistor Q and improves the rise of the output when an ECL-TTL level conversion circuit is constructed using one ordinary transistor. .

Although the level conversion circuit shown in FIG. 3 is not publicly known, it is a technique studied by the present inventor, and its outline is as follows.

In other words, the output node n□ on the NOR side of the ECL type input stage
A common collector type transistor Qxtt Qzi is connected to the output node n2 on the OR side. And transistor Q1□ and Qi! Between the emitter terminal of and the power supply voltage VEE, there are resistors R, , , R, and R,1,R, and transistors Q i connected to each other in a current mirror.
! t Q and a constant current source consisting of 14 are connected to each other. Also, between the connection node n3 of the two emitter resistors R11 and R□1 of the transistor Qli and the phase split transistor Q, the base and the Jl terminal, Q1
A diode D is connected between the connection node n4 of the two emitter resistors R2□ and R1 of the transistor Q1□ and the collector terminal (node ni) of the phase split transistor Q1.
It connects.

In the above level conversion circuit, the phase split
When the base potential of the transistor Q6 is high, the transistor Q6 is turned on and a large collector current flows, so that the collector voltage of the transistor Q6 decreases due to the voltage drop across the collector resistor Rc.

Then, when the collector voltage of the transistor Q6 becomes lower than the base voltage and saturation is about to occur, a current flows from the node n4 toward the collector terminal of Q through the diode D□. At this time, a constant current continues to flow through the resistor R22 by the transistor Qi as a constant current source connected in a current mirror. Therefore, the current flowing through the diode D1 increases the current flowing through the resistor R21.

As a result, the potential of node n drops and transistor Q
Since the base potential of , decreases, the collector current of transistor Q, decreases. by this.

The amount of voltage drop across the collector resistor Rcl decreases, and the collector potential increases. Therefore, in the circuit shown in Figure 3,
When transistor Q is on, feedback is raised so that its collector potential does not become too low compared to its base potential, thereby preventing saturation.

[Problems to be Solved by the Invention] In the level conversion circuit shown in FIG. Saturation of transistor Q6 can be prevented. However, the circuit shown in FIG. 3 cannot prevent saturation of the low-side output transistor Q constituting the output stage, and therefore the rise speed of the output signal is not sufficiently improved.

Note that the transistor Q uses the diode D1.

Using the same technique as in FIG. 3 to prevent saturation of, for example, diode D4 and transistor Q,
A second diode is connected between the connection node n, which is connected to the collector terminal of the output transistor Q, and the collector terminal of the output transistor Q.

It is also possible to prevent the saturation of

However, simulations conducted by the present inventor have revealed that the provision of such a diode makes the circuit more likely to oscillate. , we have developed an ECL-TTL level conversion circuit that can prevent delays in the rise of the output due to output transistor saturation and avoid circuit oscillation even if the output stage outputs TTL level signals using ordinary transistors. It is about providing.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, common collector transistors are connected to the NOR side and OR side output nodes of the ECL input stage, and a resistor and a constant current source are connected to the emitter terminals of these transistors.
The transistors are divided into those that drive the high-side output transistor and those that drive the low-side output transistor, and the constant current path in the previous stage is also divided into two corresponding to these two phase split transistors. However, a diode is connected between each constant current path and the collector terminal of the high-side phase split transistor and the collector terminal of the low-side output transistor.

[Operation] According to the above-described means, when the low-side output transistor is turned on and the collector potential drops.

Feedback is applied to lower the base potential by causing current to flow from the constant current path in the previous stage to the collector terminal via each diode, thereby preventing saturation of the output transistor and eliminating the need to use a Schottky transistor. The present invention achieves the above object of configuring an ECL-TTL level conversion circuit in which the output rises sharply and there is no possibility of oscillation.

[Embodiment] FIG. 1 shows an embodiment of an ECL-TTL level conversion circuit according to the present invention.

The circuit of this example is similar to the circuit shown in FIG.
It is composed of an ECL type input stage C8, a level conversion section LS, and a totem pole type output stage oP.

In this embodiment, high-side and low-side output transistors Q and Q constitute the output stage oP.

The phase split transistor Q6 is divided into two parts, Q,' and Q6', so that they can be driven separately. In addition, an extra transistor Q14 connected to the constant current transistor Q It is divided into. In other words, by connecting the two transistors Q□J and Q,' to the transistor Qza in a current mirror manner, there are two constant current paths through which a current of the same magnitude as the collector current flowing through the transistors Q and 3 flows.
There are one. Further, the transistor Q□2 on the constant current path receiving the potential of the OR side output node n2 of the ECL input stage C8 is also divided into Ql,' and Q,'.

Then, between the node n4 of one constant current path and the collector terminal (node ni) of the transistor Q1, saturation of the phase split transistor Q,' that drives the high side output transistor Q of the output stage is prevented. A diode D2 is connected for this purpose. This turns on the transistor Q,' and its collector resistance Rc,
When the potential of node n decreases due to the voltage drop at node n, and transistor Q,' becomes about to be saturated, current flows from node n4 to node n through diode D1, and the potential of node n4 and the base potential of transistor Q1 decrease. This makes saturation less likely to occur. on the other hand,
When the end-to-black position falls too low.

Since the transistor Q@' moves toward the cut-off direction, the collector current decreases, the potential of the node n increases, and the current flowing from the diode D1 to the node n decreases. As a result, the base of transistor Q,j rises. In this way, node n4. By connecting the diode D4 between n6, the transistor Q,'
Feedback is applied between the base and collector of the transistor Q1, and the potential of the node n5 is maintained at a low potential that does not cause saturation of the transistor Q1.

Regarding the phase split transistor Q6'' that drives the low side output transistor Q of the output stage OP,
Saturation is prevented by omitting the collector resistor. However, in order to adjust the collector current of transistors Q and IP, a collector resistor with a small resistance value that does not saturate Q and TI may be inserted.
On the other phase split transistor Q,' side, a voltage that cuts off the high side output transistor Q is generated at the node n, so the collector resistance Rc@' cannot be made very small, but the transistors Q, H The side collector resistance can be made small or omitted.

Furthermore, a diode-connected transistor Q is connected between the emitter terminal of the transistor Q and the power supply voltage VEE.
1° is provided. This transistor Q1° acts as a clamp diode that clamps the base voltage of the output transistor Q, and suppresses the saturation of the transistor Q.

However, if the transistor Q is not a Schottky type transistor but is constituted by a normal transistor.

Transistor Q1° alone cannot completely prevent its saturation operation.

Therefore, in this embodiment, a resistor R on the second constant current path before the phase split transistor Q19 is used.
A diode D2.2,' is connected between the connection node n of R1' and the collector terminal of the output transistor Q. D, are connected in series. The reason why the diodes are connected in two stages is that there is one stage of the double split transistor Q6' between the constant current path and the output transistor Q, where the voltage drop corresponding to the base-emitter voltage VBE is Because there is, it is to match it.

In this way, node 11. If diodes D,, D, are connected between the collector terminals of and transistor Q, then
Output transistor Q, is turned on.

When the output voltage Vout drops considerably and the transistor Q is about to be saturated, a current flows from the node n to the collector terminal of the transistor Q9 through the diode 029D. And the current is resistor R1"
increase the current flowing to the

Therefore, the amount of voltage drop across resistor R31' increases,
The base potential of transistors Q and 'Q.

lowers the base potential of As a result, the output transistor Q shifts to the cutoff direction and the collector current decreases. As a result, the output voltage Vout, that is, the collector potential of the transistor Q, drops extremely, causing Q,
is prevented from becoming saturated. On the other hand, if the base potential of the output transistor Q falls too much, the collector potential rises and the current flowing into the output terminal through the diodes D, D, decreases. Therefore, contrary to the above, the base potential of the transistor Q increases.

In this way, in this embodiment, since the diodes D2 and D3 are provided, when the collector potential of the output transistor Q falls, it is raised.

Furthermore, if the collector potential rises too much, feedback is applied to lower it. As a result, the output transistor Q,
saturation operation is prevented. the result.

When the input signal Vin changes, the output transistor Q.

When the switch changes from on to off, its operation occurs quickly, and the rise of the output voltage becomes steep.

Moreover, the phase split transistor Q,
Separate constant current paths are provided corresponding to l and output transistor Q, and diodes D□ and D2 are provided between each constant current path and the collector terminals of transistors Q and ' and Q, respectively. Therefore, one feedback action does not affect the other feedback action, so there is no risk of the circuit oscillating.

Note that in the above embodiment, the output transistor Q.

Between the base terminal of the transistor Q and the power supply voltage VEE, there is a transistor Q which acts as a diode and speeds up the extraction of the charge accumulated in the base. Although a base resistor R11 and a collector resistor R1□ are provided, it is also possible to simply replace these with one resistor.

As explained above, the above embodiment includes an ECL type input stage,
A common-collector transistor is connected to the output nodes on the OR side and the OR side, and a resistor and a constant current source are connected to the emitter terminals of these transistors, and a phase split transistor is used to drive the high-side output transistor. The constant current path in the previous stage is also divided into two corresponding to these two phase split transistors, and the constant current path and the high side output transistor are divided into two. Since a diode is connected between the collector terminal of the phase split transistor on the side and the collector terminal of the output transistor on the low side, when the output transistor on the low side is turned on and the collector potential decreases, the current is removed from the constant current path of the previous stage. Current flows to the collector terminal through each diode, and feedback is applied to lower the base potential, which prevents the output transistor from saturating and allows the output to rise sharply without using a Schottky transistor. This has the effect that it is possible to configure a level conversion/conversion circuit that is free from oscillation and is free from oscillation.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the high-side output transistor is composed of Darlington-connected transistors Q7 and Q, but transistor Q7 is omitted and a diode is connected between the emitter terminal and output terminal of transistor Q1. It can also be applied to an ECL-TTL level conversion circuit having an original totem pole type output stage.

In the above explanation, the invention made by the present inventor was mainly applied to an ECL-TTL level conversion circuit, which is the background field of application, but the present invention is not limited thereto; It can be used in general logic circuits in which the output stage is configured in a totem pole type and is capable of outputting TTL level signals.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a level conversion circuit consisting of an ECL type input stage, a totem pole type output stage, and a phase inversion transistor provided between the input stage and the output stage, saturation of the output transistor can be prevented. In addition, it is possible to configure a level conversion circuit in which the output has a steep rise without using Schottky transistors and is free from oscillation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an ECL-TTL level conversion circuit according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional ECL-TTL level conversion circuit. FIG. 3 is a circuit diagram showing an example of an ECL-TTL level conversion circuit studied prior to the present invention. C8...ECL type input stage, S...level shift stage, op...output stage, Qst Q@' j Q@
"...Phase inversion transistor (phase split transistor), Ql...High side output transistor, Q,...Low side output transistor. Q1seQi**Q□4' l Qx*7... ... Constant current transistor, D,, D,, D, ... diode. Fig. 1

Claims (1)

[Claims] 1. An ECL type input stage, a totem pole type output stage,
A level conversion circuit comprising a phase inversion transistor provided between the input stage and the output stage, the level conversion circuit comprising:
The pair of output nodes of the L-type input stage are connected to common-collector transistors each having a resistor and a constant current source connected in series between the emitter terminal and the low-side power supply voltage terminal of the circuit to form a constant current path. A level conversion circuit comprising: a diode connected between the constant current path and the collector terminal of the phase inversion transistor or the low-side output transistor of the output stage. 2. The phase inversion transistor is divided into one for driving the high-side output transistor of the output stage and one for driving the low-side output transistor, and correspondingly, constant current paths are also provided separately. and each constant current path,
The level according to claim 1, characterized in that a diode is connected between the collector terminal of the phase inversion transistor that drives the high-side output transistor and the collector terminal of the low-side output transistor, respectively. conversion circuit. 3. The device according to claim 1 or 2, characterized in that two diodes are connected in series between the constant current path and the collector terminal of the low-side output transistor of the output stage. Level conversion circuit.