JPS63128670A - Manufacture of isolation - Google Patents

Abstract

PURPOSE:To form an extremely narrow isolating region for the realization of an enhanced integration by a method wherein the middle one of three layers vertically installed on a semiconductor substrate is removed for the creation of a gap equivalent in thickness to the removed layer and an insulating layer of silicon oxide is built in the gap. CONSTITUTION:On the surface of a P<->-type semiconductor substrate 1, a SiO2 layer 5, nitride film 6, and a polycrystalline silicon layer 7 of appropriate dimensions are formed. Further, a polycrystalline silicon oxide film 8 is deposited and a nitride film 9 is formed by vapor growth. A process follows wherein the nitride film 9 is so etched that it will be as wide as the width W of the nitride film T and then the oxide film 8 is removed. The result is a gap 10, formed between the ends of the nitride films 7 and 9, with its depth equivalent to the thickness (DELTAl=0.2mum) of the now-removed oxide film 8. The nitride film 9 is then removed by etching, when a part of the nitride film 6 exposed in the gap 10 is removed at the same time. After this, the polycrystalline silicon layer 7 is also removed. A process follows wherein thermal oxidation is accomplished for the formation of an SiO2 insulating layer 11 in the gap 10. Finally, the nitride film 6 and SiO2 film 5 are removed, for the exposure of the surface of the P<->-type semiconductor substrate 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing isolation provided for electrically isolating a plurality of semiconductor elements from each other in a semiconductor integrated circuit.

[Conventional example]

The conventional isolation structure is C0D (
The case of charge transfer denoise will be explained. In the figure, a comb-shaped portion 1 indicated by diagonal lines is an isolation region f, which is formed by diffusing highly concentrated impurities from the surface of the semiconductor substrate toward the inside. A plurality of transfer electrodes 2 are formed on the upper surface of the semiconductor substrate via a gate oxide film (not shown), and isolation regions 1
A charge transfer channel 6 is formed under the transfer electrode 20 except for the transfer electrode 20 . Then, a transfer drive signal Φ is applied to each transfer electrode 2.
When applying ■, ~Φ■4, the signal charge is transferred from K,
Further, adjacent transfer channels 3 are electrically separated by isolation f, so that signal charges always move through a predetermined transfer channel 3.

[Problem that the invention seeks to solve]

However, in isolation of such a structure, photolithography (Photo□-I it
hography ) K is formed by the minimum width! (See Figure 9) is 1 to 2 μm in normal manufacturing process 1,
Even in a high-density manufacturing process, there is a limit f of about 0.8 μm, making it difficult to develop, for example, solid-state image sensors and other electronic circuit devices that aim to achieve high density and high pixel density.

[Means for solving problems]

The present invention has been made in view of the above problems, and an object thereof is to provide a method for manufacturing an extremely narrow isolation.

In order to achieve this object, the present invention forms a first layer on the upper surface of a semiconductor substrate, stacks a second layer on at least a side end surface of the first layer, and further laminates a second layer on at least a side end surface of the second layer. a first step of forming at least three layers disposed relative KW to the horizontal plane of the semiconductor substrate by laminating a third layer on the first layer; a third layer interposed between the second layer
a second step of forming a gap corresponding to the thickness of the third layer; and thermal oxidation through the gap to form an insulating layer made of silicon oxide in the semiconductor substrate. It is characterized by comprising a third step of forming.

〔Example〕

An embodiment of the isolation manufacturing method according to the present invention will be described below with reference to the drawings. FIGS. 1 to 8 are longitudinal cross-sectional views of main parts sequentially showing a series of manufacturing steps.

The manufacturing method and structure will be explained based on these drawings. First, in the first manufacturing process, as shown in FIG. Si02)5 and nitride film (Si3
N2) 6 is laminated, and a polysilicon layer 7 of an appropriate shape is further deposited on the upper surface. For example, when forming a CCD,
In the second manufacturing process, the length and width W are designed according to the shape of the transfer channel to be formed, as shown in FIG. As an example, the thickness of the silicon oxide film 5 is 25 OA.

The thickness of the nitride film 6 is 1500A, the thickness of the polysilicon layer 7 is 500X, and the thickness of the polyoxide film 8 is about 0.2 μm.Next, in the third manufacturing process shown in FIG. Approximately 150
A nitride film 9 having a thickness of OA is deposited by vapor phase growth.

In the fourth manufacturing step shown in FIG. 4, a portion of the nitride film 9 that is approximately the same width W as the previously formed nitride film 7 is removed by etching to expose the upper end surface of the polyoxide film 8. let

In the fifth manufacturing process shown in FIG.
is removed by etching to expose the surface of the nitride film 7. As a result, a gap 10 corresponding to the thickness of the polyoxide film 8 by Δl''=0.2 μm) is formed between the side edges of the nitride films 7 and 9.

Next, in a third manufacturing step t shown in FIG. 3, the nitride film 9 is removed by etching to expose the surface of the nitride film 60. At this time, a portion of the nitride film 6 exposed in the gap 10 is also etched at the same time, and a portion of the silicon oxide film 7 is exposed at the width Δ4 of the gap 10, as shown in FIG.

Thereafter, polysilicon layer 7 is removed by etching.

Next, in a seventh step, insulating layers 11 of silicon dioxide (Si02) are formed in the semiconductor substrate by thermal oxidation, for example, wet oxidation, as shown in FIG. 1, which is formed through the uncovered portion, that is, the gap 1o, and the depth Δh is 0.4.
When designed to be ~0.5 μm, it is possible to set the width ΔW to Q, about 2 pm.

Final step f for isolation manufacturing shown in Figure 8
Then, the nitride film 6 and silicon oxide film 5 are removed by etching to expose the surface of the semiconductor substrate 40.

After passing through the above manufacturing steps, CCDs and the like are manufactured. For example, when forming a COD, a Vcn- type impurity layer is formed on the surface of the semiconductor substrate 4 by thermal diffusion or ion implantation, then a gate oxide film is formed, and then a transfer electrode made of polysilicon or the like is formed. As a result, the insulating layer 1
A COD is formed in which 1 is an isolation region and the impurity layer is a transfer channel.

As described above, according to this embodiment, the width of the insulating layer 11 can be made much narrower than that of the isolation region 1 (see FIG. 9) made of the conventional impurity diffusion layer, which is effective in improving the degree of integration. be. or.

Since the insulating layer 11 itself does not have conductivity, isolation is performed using the depletion layer, eliminating the need for wiring as in the case of 5, and further increasing the degree of integration. [Effects] As explained above, according to the present invention, a first layer is formed on the upper surface of a semiconductor substrate, a second layer is laminated on at least the side end surface of the first layer, and a first step of forming at least six layers disposed relative to a horizontal surface of the semiconductor substrate by laminating a third layer on at least a side end surface; When the third layer interposed between the second layers is removed, a second step of forming a gap corresponding to the thickness of the third layer, and thermal oxidation through the gap, A third step of forming an insulating layer made of silicon oxide in the semiconductor substrate, and forming an insulating layer corresponding to the thickness of the second layer in the semiconductor substrate as an isolation region. 1. It is possible to realize an extremely narrow isolation region, and it is possible to further increase the degree of integration of semiconductor integrated circuits.

[Brief explanation of the drawing]

1 to 8 are longitudinal cross-sectional views of main parts showing the manufacturing process in an embodiment of the isolation manufacturing method according to the present invention, and FIG. 9 is a plan view of main parts showing the conventional isolation structure in the case of COD. There is Figure 1. 4... Semiconductor substrate, 5... Silicon oxide film,
6...Nitride film, 7...Polysilicon layer. 8...Polyoxide film, 9...Nitride film. 10... Gap, 11... Insulating layer. (3 others) iE1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 3 Figure 7 Figure 9

Claims (2)

[Claims] (1) Forming a first layer on the upper surface of a semiconductor substrate, laminating a second layer on at least a side end surface of the first layer, and further laminating a third layer on at least a side end surface of the second layer. By doing so, a first step of forming at least three layers standing upright relative to the horizontal surface of the semiconductor substrate, and a third layer interposed between the first and second layers are performed. a second step of forming a gap corresponding to the thickness of the third layer by removing the third layer; and a second step of growing an insulating layer made of silicon oxide within the semiconductor substrate by thermal oxidation through the gap. A method for manufacturing isolation, comprising the steps of 3. (2) In the first step, a silicon oxide film and a first nitride film are laminated on the surface of the semiconductor substrate, and the first layer made of a polysilicon layer having a predetermined shape is formed on the upper surface of the nitride film. and forming the second layer made of a polyoxide film formed by oxidation on at least the side end faces of the first layer, and further comprising another nitride film on at least the side end faces of the second layer. The second step includes the step of stacking the third layer, and the second step includes removing the upper end of the third layer by etching to expose the second layer, and then stacking the second layer. The third step includes forming the gap in the first nitride film by etching to reach the silicon oxide film through the gap, and forming the gap in the first nitride film by etching. 2. The isolation manufacturing method according to claim 1, wherein the insulating layer made of silicon oxide is formed in the semiconductor substrate by thermal oxidation through the gap formed in the nitride film.