JPS63127637A - Digital signal transmitter - Google Patents

Abstract

PURPOSE:To identify a word with high reliability by correcting the phase of a clock signal according to a predetermined logic condition relating to information sent at a reception side so as to establish the synchronization with the received word with high reliability without the provision of synchronizing information at the sender side. CONSTITUTION:A counter 7 is connected respectively to an output corresponding to an LSB (D0 in 8-bit), an intermediate location bit (D4 in 8-bit) and an MSB (D7 in 8-bit) and counts (C0-C4), (C4-C7) for the number of transition times of the state during the prescribed period are compared by a corresponding comparator 8 respectively. The the counts of the three counters 7 during the prescribed period are compared by the two comparators 8, and if even one of them does not satisfy condition, a control signal is generated by one bit width. Thus, the similar count and operation is repeated for a prescribed period and the processing is retarded finally till the point of time when the two comparators 8 satisfy the condition, that is, till the point of time when the word synchronization is established, and then completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal transmission device that digitizes and transmits analog waveform signals such as video signals.

[Conventional technology]

FIG. 6 is a block diagram of a conventional digital signal transmission device shown in "Optical Fiber Communication System" (page 249) edited by the Television Society of Japan. In the figure, (11 is a low-pass filter that limits the band of the video input signal (analog signal), (2) is a sampling holding circuit for the output of this low-pass p-wave filter fl+, and (3) is this sampling An encoder (A/D converter) that converts the analog signal output from the holding circuit (2) into a digital signal, (13Vi parallel-to-serial converter circuit), encoder (3)
), and inserts a frame synchronization pattern from the frame butter/generator (15) to create a frame as shown in FIG. 1, described below.

α41 is a frequency dividing circuit, which divides the clock of the clock generator αG by −±. However, n is an integer of 2 or more. θημ parallel-to-serial conversion circuit (optical transmission line that guides the output of 13,
α 穆 is a parallel-to-serial conversion circuit (connected to 13 and a nine-equalization circuit via the optical transmission line αη, 09 is an equalization circuit (identification regeneration circuit connected to the output end of Iυ, ■ is a clock regeneration circuit, etc.) An optical receiver is configured by a clock regeneration circuit (to) from the conversion circuit α rod, and regenerates an input data signal and a clock signal from the video input signal.01) Based on the clock signal of the Vi microc generation circuit A frame detection circuit that synchronizes frames based on the frame pattern in the input signal, a frequency divider circuit that divides the clock signal of the clock regeneration circuit (to) by -, and (c) a bit output of the regeneration circuit α for each ha. 04) is a serial-to-parallel conversion circuit that converts the signal into a parallel signal, 04) is a decoder (D/A converter) that converts the signal from the serial-to-parallel conversion circuit @ to an analog format signal, and (to) is the total sample output of the decoder @. 2 is an interpolation transducer that interpolates the output of the resampling circuit (to) to obtain a video output signal.

Next, the operation will be explained. Video input signal.

The signal is input to a low frequency door filter (1), where out-of-band aliasing noise components are removed, and further sampled by a sampling and holding circuit (2), where it is held for one sampling period. Next, the signal from the sampling and holding circuit (2) is digitally converted by an encoder (A/D converter) (3).

Bit parallel output. The output of the encoder (3) is serialized by the parallel-to-serial conversion circuit 0, and the frame pattern generated by the frame pattern generator α9 is also inserted.
After being formed into a given transmission frame.

The signal is sent to the optical transmission line aη.

FIG. 7 shows the entire format of the converted data output from the encoder (3) and the signal created by the parallel-to-serial conversion circuit a3. This figure shows a case where 1m bit quantization is performed, and the frame pattern t-F1=@1''.

It is composed of an alternating pattern where FO=@O”.

In this case, one word is composed of n==m+1 bits and 9
The figure shows a configuration of one frame and two words.

The signal having the format shown in Fig. 7 is converted into an optical signal, guided through a transmission line αη to other circuits α, such as those forming an optical receiver, and sent to a light receiving element (not shown). After being electrically converted, equalization is performed in a nine-equalization circuit α according to the characteristics of the transmission path. The output of the equalization circuit αl is input to the clock regeneration circuit through the identification and regeneration circuit α9, where the clock signal is regenerated. Next, the output of the equalization circuit (Il) is outputted from the identification and regeneration circuit 0, and based on the clock signal, an output of a bit series signal in a 9-element format is obtained. Frame synchronization is achieved by the detection circuit 12η and the frequency dividing circuit @, and parallel signals in a 9-element format are output from the serial/parallel conversion circuit (c).

FIG. 8 is a block diagram showing a frame synchronization and parallel multiplexing/demultiplexing circuit which is comprised of a frame detection circuit QD1 frequency dividing circuit @ and a serial/parallel conversion circuit (to). The data reproduced by the identification and reproduction circuit α1 is input to a data signal frame synchronization pattern detection circuit shown in FIG. The frame synchronization pattern detection circuit (5) compares the frame synchronization pattern created by the timing pulse generator (7) with the corresponding data input signal, and if the two do not match, it is determined that the synchronization is out of synchronization. The bit width mismatch pulse is input to AND gate 4 via the full synchronization protection circuit 2, and output of the clock signal is inhibited by 1 bit.

As a result, the supply of the clock signal to the timing pulse generator (to) is stopped by 1 bit, and the phases of the 7 frames created on the receiving side and the input frame are shifted backward by 1 bit. Thereafter, the same operation as described above is repeated, and the phases of the receiving frame and the input frame gradually approach each other, and finally, they are synchronized, that is, they are brought into alignment. In this way, once synchronization has been established, the synchronization protection circuit (to) is designed so that even if a slight error occurs in the optical transmission line 0η, it will not be easily determined to be out of synchronization! A synchronization protection function is activated to prevent erroneously determining that synchronization has been established even if the same code string as the synchronization pattern is input during synchronization verification. When synchronization is established, the serial/parallel conversion circuit (c) separates the data of each digit from the input signal into parallel signals based on the control signal from the timing pulse generator (to) and sends them to the decoder (D/ It is converted into an analog signal by the A converter) Q4), and the video output signal in the original format is reproduced through the interpolating F wave unit @.

[Problem that the invention seeks to solve]

Conventional digital signal transmission equipment is configured as described above, so when transmitting serial signals using all transmission lines, the parallel signals after analog-to-digital conversion are converted into parallel to serial, and the receiving side Inserts a frame synchronization pattern for each digit and allows for complete identification of timeslots.

Also, on the receiving side, υ
Since it is necessary to verify the received signal and establish frame synchronization, it is necessary to install a frame synchronization pattern generator on the transmitting side, and a complex digital signal processing circuit including a frame synchronization pattern detection circuit, a synchronization protection circuit, etc. on the receiving side. However, there are problems in that the addition of synchronization information lowers the effective transmission efficiency and increases the circuit scale.

This invention was made to solve the above-mentioned problems, and uses serial signals that are transmitted with high reliability without adding synchronization information.

It is an object of the present invention to provide a digital signal transmission device that can separate parallel signals consisting of information to be transmitted, has a simple circuit configuration for synchronization, without reducing transmission efficiency, and has a simple circuit size.

[Means to solve all problems]

The digital signal transmission device according to the present invention converts all analog information to be transmitted into digital signals on the transmitting side, organizes the signals into a series of words each consisting of a plurality of serial bits, and transmits the signals.

On the receiving side, one word of the digital signal sequentially received by a serial-to-parallel conversion circuit is stored in accordance with a clock signal synchronized with the digital signal.

A plurality of counters count the number of logical state transitions in the most significant bit, intermediate bit, and least significant bit of the buffer register that occur within a predetermined period according to the clock signal, and the number of transitions between these counters is calculated. Numerical values are compared by multiple comparators, and the outputs of these comparators control the sequencer to correct the phase of the clock signal according to predetermined logical conditions related to the information to be transmitted. be.

[Effect]

The digital signal transmission device in this invention is:

On the receiving side, count the number of logical state transitions that occur in the most significant bit, intermediate bit, and least significant bit stored in the serial-to-parallel conversion circuit within a predetermined period, compare the counts, and calculate the comparison result. Since the phase of the clock signal is corrected according to the above, there is no need to add synchronization information on the transmitting side.

A reliable synchronization is established for the received word and the word is reliably identified.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the configuration of the transmitting side of the digital signal transmission device of the present invention.

(1) is a low-frequency F-wave device that receives an input signal, and (2) is a sampling and holding circuit that introduces the output of the low-frequency F-wave device (11).

(3) is an encoder that encodes the output of the sampling and holding circuit (2).

(4) is a parallel-to-serial conversion circuit that converts the output of the encoder (3) into a bit-serial signal; (5) is a sampling and holding circuit (2) that divides the clock signal; an encoder (3); This is a frequency divider that supplies the parallel to serial conversion circuit (4). FIG. 2 is a block diagram showing the configuration of the receiving side in the digital signal transmission apparatus of the present invention. (6) is a serial-to-parallel conversion circuit that inputs a data input signal (serial) to a clock signal and converts it into a parallel signal, and (7) is the highest level of the parallel separated signals of this serial-to-parallel conversion circuit (6). A counter that counts the transitions of the logic states of the bit (MSB), least significant bit (LSB), and intermediate bit.

(8) is a comparator that compares the count values of the outputs of adjacent counters (7), (8a) is an or game that takes the logical interest of comparator (8), and (9) is a clock signal input. , a sequencer that generates various clock signals (timing signals); (9a) is provided at the input end of the sequencer (9); an AND gate leads the output of the OR gate (8a) to the inverting input, and the output of the OR gate (8a) is connected to the input clock and logic. Take the product.

Next, the operation on the transmitting side will be explained. Various analog signals, such as video signals, characterized by changes in waveforms are input as input signals to a low frequency door filter fil, and frequency components outside the transmission band are removed. Next, the signal of the low-frequency wave filter (11) is converted into a digitalized bit-parallel signal by the sampling and holding circuit (2) and the encoder (3).The signal of the encoder (3) is converted to a bit parallel signal by the frequency divider ( Parallel/serial conversion circuit (4)
) and is converted into a bit-serial signal as shown in FIG. What should be noted here is that no circuit is provided for inserting an additional biller for the word period.

Next, the operation on the receiving side of the present invention will be explained. The signal transmitted as a serial signal on the transmitting side as shown in FIG. 4 becomes a data input signal on the receiving side as shown in FIG. This data input signal is input to the serial/parallel conversion circuit (6), and the sequencer (9) is controlled by the input clock signal.
) is converted into a υ-bit parallel signal by the clock signal from

In this case, it should be noted that specific digits are not necessarily determined and output to the parallel output circuit by identifying the correct word from the bit-serial signal; for example, when the power is turned on, etc. Depending on the conditions at the start of operation, errors may occur. Now, if the information signal to be transmitted is not encoded with a random amplitude occurrence probability, but is linearly quantum encoded as represented by the video signal shown in Figure 3, each quantized digit is A signal can be considered that is characterized by the number of time-averaged logic state transitions.

Figure 3 shows the simplest case of such a signal, in which the three digits (M
SB, middle bit, LSB) shows the transition of the logic state. The MSB indicates O2, the middle bit indicates Δ, and the LSB indicates ×.As is clear from the figure, when averaging over 9 hours with a video signal, f is originally due to the waveform characteristics of the signal.
i, there is a relationship of "number of transitions J of LsH > number of transitions of rMsn". In this invention, by utilizing the signal characteristics of the information to be transmitted, it is possible to obtain transmission reliability equivalent to conventional methods without adding word synchronization or frame synchronization functions. .

Here, as shown in FIG. 2, the LSB (in the case of 8-bit linear quantization, the position of pDo) is determined in advance.

A counter (7) is connected to the output corresponding to the intermediate position bit (8-bit D4) and MSB (8-bit D7), respectively, and the count value (C
o=Ca)-(C4*Cy)t- are compared by corresponding comparators (8). This makes it possible to determine whether or not the digit output corresponding to the parallel path set in advance is being output as described above. This mechanism will be explained using FIG. 4.

In the case of 8-bit quantization, the 8 combinations shown in FIG. 4 are possible as the quantized 8-bit output. As mentioned above, if the number of logical state transitions of each digit Dn is 1TDn, 'r,,n>Tnn+a. Therefore, between the two sets of count values, that is, CO→C4°C4→C7, m Co>C4 If the relationship >C7 does not hold, normal word synchronization has not been achieved, and the example shown on the left in FIG. 3 is fi7.

In this case, either one of the two comparator (8) conditions
The individual does not satisfy the conditions.

The comparison result of the two comparators (8) satisfies the conditions only in the rightmost example of FIG. In this way, the count values of the three counters (7) during a certain period of time are calculated by the two comparators (
8), and if even one of them does not satisfy the conditions, a control signal of 1 bit width is generated (OR gate (8) in Figure 2).
(9a) is closed, and the supply of the clock input to the sequencer (9) for one bit is stopped. In such a case, use the sequencer (9)
Since the supply is stopped by 1 bit, the clock signal for parallel separation is generated with a 1 bit delay, so the output of the serial/parallel conversion circuit (8) is shifted by 1 digit. It will now be output to the position.

In this way, the same counting and operation are repeated for a certain period of time, and finally the two comparators (8) are delayed until the time when the conditions are satisfied, that is, when word synchronization is established. and ends. Serial-to-parallel conversion circuit with established synchronization (8
) is supplied to the next stage decoder (not shown) in the same manner as in the conventional system, and the analog signal in the original format is reproduced.

Figure 5 is a waveform diagram of each part of the friend receiving side explained above, υ,
Corresponding portions of each waveform are indicated by A-G in FIG.

In the above embodiment, the transmission signal is a video signal, but in the present invention, the transmission waveform does not have randomness, but has a characteristic waveform.

It goes without saying that the present invention can also be applied to signals in which the frequency of state transitions of each quantized digit differs when subjected to quantum encoding.

〔Effect of the invention〕

As described above, according to the present invention, the phase of the clock signal is corrected in accordance with predetermined logical conditions regarding the information to be transmitted on the receiving side, so that the digital signal to be transmitted on the transmitting side is corrected. Word synchronization can be increased with high reliability on the receiving side without adding any additional information for word synchronization, which simplifies the configuration of digital signal transmission equipment and improves transmission efficiency. This has the effect that improvements in can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the transmitting side of a digital signal transmission device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the receiving side of a digital signal transmission device according to an embodiment of the present invention, which is provided corresponding to the transmitting side shown in FIG. 1, and FIG. A transition diagram showing the transition of the logical state of information to be transmitted on the side, FIG. 4 is a diagram showing the counter shown in FIG. 2 and its contents,
FIG. 5 is a waveform diagram of the operation of each part on the receiving side shown in FIG. 2, FIG. 6 is a block diagram showing the configuration of the transmitting side of a conventional digital signal transmission device, and FIG. FIG. 8 is a timing diagram illustrating the operation of the signal transmission device, and is a block diagram of the receiving side in the digital signal transmission device shown in FIG. 6. In the figure, (6) is a serial/parallel conversion circuit, and (7) is a counter. (8) is a comparator and a (91Vi sequencer). In FIG. 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A digital signal transmission device that converts an analog signal having a predetermined waveform into a digital signal, organizes it into a series of words each consisting of a plurality of serial bits, and transmits the data.
a serial-to-parallel conversion circuit for storing one word of the digital signal that is sequentially received according to a clock signal controlled to be synchronized with an input clock signal related to the digital signal; a plurality of counters each counting the logic state transitions occurring in the most significant bit, intermediate bit, and least significant bit of the buffer register; and an output of the counter counting the transitions of the most significant bit and the intermediate bit. a plurality of comparators that perform comparisons between the outputs of the counters that count the transitions of the intermediate and least significant bits; A digital signal transmission device, characterized in that a sequencer for controlling the phase of the clock signal according to predetermined logic conditions and each comparison result of the comparator is provided on the receiving side of the digital signal.