JPS63127560A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To decrease the number of pins by connecting a terminal outputting a measuring signal and a terminal inputting a test pattern in common while changing over the measuring signal and a test pattern signal. CONSTITUTION:When a bidirectional pin 17 is used for shift-in when a shift mode is brought, pulses are applied to a clock C1 for a shift at a time earlier than a clock C2 for the shift, and a tri-state buffer 18 is brought to 0, and closed. When the pin 17 is employed for shift out, pulses are applied to the clock C2 at a time earlier than the clock C1, the tri-state buffer 18 is opened, and a signal from a shift register is output. Since the tri-state buffer is closed at the time of the shift-in by these operation, the signal from the shift register and the signal of the shift-in do not collide. Since the try state buffer 18 is opened on the shift-out, the signal from the shift register is extracted from the bidirectional pin 17. Accordingly, the number of pins can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and is one of methods for designing for testability. 3 in scan design design,
This relates to eliminating pin necks.

[Conventional technology]

For example, Figure 4 shows a semiconductor integrated circuit device using the conventional scan canvas method.
Via the shift register launch (hereinafter referred to as SRL) of (2) to (8), the scan out terminal (9), the input terminal α071), etc., the internal circuit 0υ, and the shift register launch 131, +4). Internal circuit @, again.

An output α/\ circuit is constructed via the shift register lunch (7) and an internal circuit (to).

Next, the operation will be explained. To test the shift register, apply a test pattern from the scan-in terminal (1) and observe the test result at the scan-at terminal (9) via the shift register latches (8) to (8). Check normal operation. Next, to test the internal circuit (b), apply the test pattern to the input α01, take the test result of the internal circuit Ql) into the shift register launch +3), +4), and use the shift register to send the test pattern to the scan out terminal (9). and observe the results. Next, the test of the internal circuit @ is the shift register launch (2) to (4) which is the input of the internal circuit a.
A test pattern is input using the shift register from the scan-in terminal (1) of Iko (1), and the test results of the internal circuit @ for the test pattern are taken into the shift register lunch +7) and (8).

Use a shift register to pull out to the scan at terminal (9) and observe the result. Next, the test for the internal circuit (to) is similar to that for the internal circuit @.

Observe the test results of the internal circuit (to) using the direct 1F) output α.

Next, Figure 2 shows a design method called Level Sensitive Tapescan Design (LSSD).
) corresponds to the 77 register launch (SRL), and prevents the operation from becoming unstable due to signal rise time, rise time and circuit delay time.

The clock is multiphased into a shift clock (C1) and a shift clock (C2).

Furthermore, by connecting the 5RL8 as shown in FIG. 3, the shift register shown in FIG. 4 is constructed.

[Problem that the invention seeks to solve]

Since the conventional semiconductor integrated circuit device has the above-described structure, a total of 2 bins of scan-in terminal C1) and scan-out terminal (9) are required for cyst-in or cyst-out, reducing the number of bins. It is necessary to.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device that can reduce the number of bins.

[Means for solving problems]

The semiconductor integrated circuit device according to the present invention includes a terminal for outputting a measurement signal and a terminal for inputting a test pattern, and a signal switching means for switching between the measurement signal and the test pattern signal. It is something that

[Effect]

According to the third aspect of the present invention, the terminal for outputting the measurement signal and the terminal for inputting the test signal can be connected in 8 # ways by the signal switching means.

[Embodiment] An embodiment of the present invention will be described above with reference to the drawings. 18
In FIG. 1, (2) to (8) and (10 to α41) are completely the same as those in the conventional device, and their explanations will be omitted.

(SM) is a shift mode signal; when it is 1, it is the shift mode, and when it is 0, it is normal operation.
The signals from 9 and 1 and the shift clock (C1) are input to the JK flimp flop (20a), and its output is input to the AN
D gate (15c) 1 is input. Similarly, the signal (S
M), the signal from the power supply (111), and the clock for shifting (CI) are input to the JK flimp-flop (201), whose output enters the inverter α.
It is input to the ND gate (15c), and the AND gate (15
The output of C) goes into the - tristate buffer. The tri-state buffer calm opens when the signal is 1 and closes when the signal is 0. αη is a bidirectional bin for shift-in and shift-out. Here, JK Flimp 70g (
20a), (2(lb), the signal is inverted at the rising edge of the pulse.

In the semiconductor integrated circuit device configured as described above, J is connected to the power supply 091, so the signal is always 1.
It is. When (SM) becomes 0 due to normal operation,
When a pulse is applied to (C,), (Q,) becomes 1. Similarly, (Qt) becomes 1, and JK Fullingf a 7
7' (20a) The initialization of the JK flimp frog (20b) is completed.

Next, consider when (SM) is in shift mode 1.

When the bidirectional bin qη is for shift-in, (C
In case 1), pulses are applied faster than in case (C2).

When a pulse is applied to (CI), (Q,) becomes O and when that signal enters the AND gate (15a), (C
, ), even if a pulse is applied after that, AND()
Since the output of (15a) is 0, (Q,) is held at 0. In the JK Frigg Frog (20b), since the application of the (C1) Yorimo pulse is slower in the case of (C), when (Q,) is 0, -(Q,) #c is held at 1, and The signal is inverted by inverter α0 and becomes 0, and the signal enters the AND game of that signal (15b), so even if a pulse is applied to (C2) from then on, (Q
R) holds 1.

Therefore, when the bidirectional bin aη is used for shift-in, the tri-state buffer becomes O and closes.

Next, normal operation occurs, so (SM) becomes 0, and the outputs (Q,) and (Q,) become 1 as before.

Next, consider a case where (SM) is in shift mode 1 and bidirectional bin ση is in shift-out mode.

When it is for shift out, (C2) is better than (C
1) Pulses are applied faster. When a pulse is applied to (C6), (Q becomes O and its output becomes A
(ND gate) Once entered (15b), even if a pulse is applied to (Ct) after that, the output of AND gate (15b) becomes 0, so (C2) is held at 0, and inverter α・
is reversed.

When the output 1 enters the AND gate (15c), the tristate amplifier (to) always becomes 1 and opens. That is, when the bidirectional bin αη is for shift out, the tristate buffer (to) is opened and the signal from the shift register is output. As a result of the above operation, the tri-state amplifier closes during shift-in, so that the signal from the shift register and the shift-in signal do not conflict with each other. Furthermore, at the time of shift-out, the tri-state buffer (2) is opened, so that the signal from the shift register is taken out from the bidirectional bin (1).

This invention is not limited to the above-mentioned embodiments;
For example, in the circuit that sends the tri-state pan 7-ar 4-l signal, when the bi-directional pin is for shift-in, the signal is O, and when it is for shift-out, the signal is 1.
It is also possible to use a circuit that can control shift-in to scan path and shift-out mode switching from scan path using only a shift clock and a shift mode signal.

〔Effect of the invention〕

As described above, according to the present invention, the terminal for outputting the measurement signal and the terminal for inputting the test pattern are commonly connected, and the measurement signal and the test pattern signal are switched. Since the signal switching means is provided, it has an excellent effect in that the number of bins can be reduced.

[Brief explanation of the drawing]

Figure @1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, Figure 4 is a circuit diagram showing a conventional semiconductor integrated circuit device, and Figure @2 is a circuit diagram showing a notation for shift register lunch. , @3 is a circuit diagram showing a shift register. In the figure, (1) is a scan-in terminal, (2) to (
8) Ha shift register latch, (b) to (to) are internal circuits, - to (150) are AND gates, (to) are inverters, Qη is a bidirectional bin, C81 is a tri-state buffer, (19 is a power supply, (20a) and (20b) are the JK7 logic amplifier A7, (SM) is the shift mode signal, (C,) and (C,) are the shift clocks. 3. The same symbols in each figure are the same, or A considerable portion is shown.

Claims (1)

[Claims] A circuit under test that is measured using the scan design method, a terminal that outputs a measurement signal output from this circuit under test,
A semiconductor integrated circuit device comprising: a signal switching means commonly connected to a terminal for inputting a test pattern to the circuit under test, and switching between the measurement signal and the test pattern signal.