JPS63127171A - Ic testing apparatus - Google Patents

Abstract

PURPOSE:To enhance efficiency, by selecting the output of a normal clock signal generator and that of a register in a time-dividing manner. CONSTITUTION:A clock signal generating apparatus 2 is constituted by connecting the respective output terminals of two registers 4, 5, a normal clock signal generator 6 and a selected signal generator 7 to the corresponding input terminals of a selector 3. The selector 3 selects the normal clock signal TS being the output of the generator 6 at the time of a normal cycle while selects the register output TA of the register in the timing of a selection signal Ta and successively selects the register output TB of the register 5 in the timing of a succeeding selection signal Tb at the time of a mode setting cycle and outputs selection output TO as an output signal. As a result, a signal TS is outputted to the output terminal of the selector 3 at the normal cycle and the outputs TA, TB are outputted at the time of the succeeding mode setting cycle as the selection output TO while the mode setting cycle is divided timewise to be inputted to th mode setting terminal of IC 11 to be measured through a testing circuit 1 to test IC.

Description

[Detailed description of the invention] Industrial application field] The present invention relates to an IC testing device.

[Conventional technology]

Recently, with the increasing integration and performance of ICs,
The conventional single function has been expanded to multi-function.

Therefore, ICs have appeared that have specific terminals (hereinafter referred to as mode setting terminals) that can set the operating mode of an element depending on the logic state at a certain point in time.

FIG. 3 is a timing diagram of an example of the mode setting terminal input signal of this IC, and Table 1 shows the signal a in FIG. 3.

It is a table showing modes based on combinations of b.

Table 1 This IC performs normal operation using a normal clock signal during normal operation (hereinafter referred to as normal cycle) according to the timing shown in Figure 3, and specifies the mode when setting the IC operation mode (hereinafter referred to as mode setting cycle). As information a, b
A statement of logic! 5 is set to one of the four modes shown in Table 1.

Therefore, testing this IC requires a mode setting terminal input signal as shown in the timing diagram of FIG.

A conventional clock signal generating device of an RC test device has a structure in which a normal clock signal is generated synchronously with a basic timing signal and at a timing set in advance according to a test program.

[Problem that the invention seeks to solve]

The above-mentioned conventional IC test equipment generates a clock signal periodically at a timing set in advance by a test program, so it is a normal clock signal generator that generates only one pulse within one cycle of a periodic basic timing signal. A multifunctional IC with a mode setting terminal
When testing, there is a problem in that, in addition to the conventional normal clock signal, it is necessary to conduct a separate test for each function set by inputting a mode setting signal.

An object of the present invention is to provide an IC testing device that can set a plurality of operation modes using a signal including a mode setting signal input, and can improve efficiency.

[Means for solving problems]

The IC testing device of the present invention includes a selection signal generator that sets the timing of a plurality of registers and a normal clock signal generator, and inputs the outputs of the registers, the normal clock signal generator, and the selection signal generator. , and a selector that sends the output of the normal signal generator to the test circuit during the normal cycle and the register output during the mode setting cycle.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The block signal generator 2 includes two registers 4 and 5, a normal clock signal generator 6, and a selection signal generator 7.
The respective output terminals of the selector 3 are connected to the corresponding input terminals of the selector 3. Further, the output terminal of the clock signal generator 2 is connected to the input terminal of the test circuit 1.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of the clock signal generating device 2 of FIG. 1.

During the normal cycle, the selector 3 selects the normal clock signal T, which is the output of the normal clock generator 6, by the selection signal T4.
s is selected, and the selection signal T is selected in the mode setting cycle.
The register output T^ of register 4 is selected at the timing of , and the register output TB of register 5 is sequentially selected at the timing of the subsequent selection signal Tb, and the selected output T is output as an output signal.
. issue.

As a result, in the normal cycle, the normal clock signal Ts is supplied to the output terminal of the selector 3, and in the following mode setting cycle, the register output TA and the register output TB are time-divided in the mode setting cycle, and the selector output To The signal is output as , and is input to the mode setting terminal of the ICII to be measured via the test circuit 1 to perform an IC test.

In the above embodiment, the number of registers is two, but the number of registers may be increased depending on the mode table of ICI 1 to be measured.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to integrate the functions of multiple modes and test an IC by selecting the outputs of the conventional normal clock generator and register in a time-sharing manner. Normally, the clock test and mode setting are not performed separately, resulting in the effect of high efficiency.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing diagram of various signals to explain the operation of the clock signal generator shown in Fig. 1, and Fig. 3 is a mode setting of the IC under test. FIG. 3 is a timing diagram of an example of a terminal input signal. 1...Test circuit, 2...Clock signal generation circuit, 3...Selector, 4.5...
Register, 6... Normal clock signal generator, 7
...Select signal generator, 8...IC test equipment, 9...IC to be measured 1TA, TB...
...Register output, T,, Tb...Selection signal, To...Selector output, Ts...Normal clock signal, T4...Selection signal .

Claims (1)

[Claims] a plurality of registers, a normal clock signal generator, a selection signal generator for setting timing of the register and the normal clock signal generator, and respective outputs of the register, the normal clock signal generator, and the selection signal generator; and a selector that sends the output of the normal signal generator to the test circuit during the normal cycle and the register output to the test circuit during the mode setting cycle.
C test equipment.