JPS63127165A - Level comparator - Google Patents

Abstract

PURPOSE:To set highly accurate level comparing voltage, by providing a level comparing circuit containing the first and second negative and positive conductive type MISFETs and the reference voltage source connected to the gate of the second MISFET through a node. CONSTITUTION:The N-channel MISFETM1 connected between a common input pin 1 and a node N3 becomes an ON-state when the voltage VP of the pin 1 exceeds the threshold value voltage VT1 of FETM1. When the reference volt age VS of a reference voltage source 31 is applied to the gate electrode of FETM2 through a node N2, the P-channel MISFETM2 connected between nodes N3, N1 becomes an ON-state only when the node voltage V3 of the node N3 is higher than the node voltage V1 of the node N1 and higher by the absolute value portion of the threthold value voltage VT2 of FETM2 than the voltage VS and a current flows to the node N1 from the pin 1. Since the node N1 is connected to the input terminal of an inverter 13, the node voltage V13 of a node N13 is reversed through the detection of the voltage V1. Hereupon, the output voltage V13 of a level comparator 30a is again reversed by an inverter 12 and the input/output voltage characteristic thereof becomes equal to node voltage V12 and a testing circuit 21 is operated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level comparator, and more particularly to a level comparator for an MIS integrated circuit.

[Conventional technology]

With the recent increase in the number of functions of integrated circuits, it has become increasingly necessary to efficiently test their functions.

For this reason, MIS integrated circuits have appeared that include, in addition to the normal circuit, a test circuit that operates a clock function at a higher clock frequency than normal, and a level comparator that sets the test mode.

FIG. 8 is a circuit diagram of an MIS integrated circuit which is an example of the application of a conventional level comparator.

The comparator circuit 11 connects an eleventh p-channel M I S between a fifteenth node N15 connected to the power supply and a grounded substrate.
+- The Mth transistor and the gate electrode are connected to common input pin 1 and the power supply voltage ■. threshold voltage VT greater than
The twelfth n-channel M I S 1-transistor M12 with I'2 is composed of a ratio circuit connected in series, the output end of which is connected to the input end of the inverter 12 via the eleventh node Nll, The output of the inverter 12 is applied as the output of the level comparator 30 to the test circuit 21 in the digital circuit 20 via the twelfth node N12.

Next, the operation of this level comparator will be explained.

FIG. 9 is an input/output voltage characteristic diagram for explaining the operation of the circuit shown in FIG. 8.

Since the gates of transistors 1 to M1 in FIG.
1) When the formula holds true, the node voltage V1□ at the node N1□ is the power supply voltage ■. The relationship of Equation (2) is established, and if Equation (3) holds true, the relationship of Equation (4) is established.

V(BL and VOL are the high level output voltage and low level output voltage of the comparator circuit 11, respectively.

V, <V. <VT12...(1)V
+ 1= V ou # V o −(2
>V Pmax> V P > V T12≧V,
-...(3)V ++# VOL
-(4) Conversely, the characteristics of the node voltage V11 with respect to the common pin input voltage ■P and the voltage ■1□ characteristics of the node N12, which is the output of the inverter 12 that receives it as input, are as shown in FIG. This is also the output characteristic of the level comparator 30.

Normally, when a digital signal voltage lower than the power supply voltage VD that satisfies the (+) equation is applied to the common input pin 1 as the common input bin voltage VP, the signal is applied to the 14th node NI
Since the signal is also input to the digital circuit 20 via the voltage level comparator 30, the normal circuit 22 operates normally, but the test circuit 21 does not operate because the output voltage of the level comparator 30 is almost zero.

In addition, when setting the test mode, the power supply voltage V is set as the common input bin voltage 2 to distinguish it from the normal digital signal.
. When an analog signal voltage that satisfies equation (3) within the range of maximum rated common input pin voltage V Pmay is applied to common input pin 1, the digital output voltage of level comparison 2S30 rises to approximately the power supply voltage VD, and the test The circuit 21 is operated, and at the same time, the normal operation of the normal circuit 22 is stopped.

FIGS. 10 and 11 are the n-channel M of FIG. 8, respectively.
FIG. 3 is a cross-sectional view of the chip of I S +-transistor M+2.

n-channel M I S +- transistor M1 in FIG.
2 is a transistor 1, which has a drain region 3a and a source region 3b on a silicon substrate 2, and has an insulating film 4 thicker than usual between a gate electrode 6 and a channel region 7; It is a kind of parasitic MIS transistor.

The M I S )-transistor shown in FIG. 11 has an insulating film with a normal thickness, but is designed to add an ion implantation process to the channel region 8 and particularly increase the impurity concentration to obtain a high threshold voltage. It is what was done.

[Problem that the invention seeks to solve]

The above-mentioned conventional level comparator uses the threshold voltage V12 of the transistor MI2 itself as the reference voltage for level comparison. Because special MIS+- transistors with large threshold voltages are required, and because some parts of regular MIS integrated circuits are specially designed and manufactured, steps due to threshold voltage variations and manufacturing process complexity are avoided. There were problems in terms of low yield and low economic efficiency.

There is also the problem that the integrated circuit may be damaged if the range between the maximum rated common input pin voltage V Pmax and the power supply voltage VD is small.

It is an object of the invention to provide a level comparator which does not use a special tIS transistor, whose threshold voltage is used as a reference voltage and which threshold voltage is higher than the supply voltage. It is in.

[Means for solving problems]

The level comparator of the present invention includes an A-D conversion circuit whose input terminal is connected to a first node, and a first circuit of one conductivity type connected in series between the signal input terminal and the first node. M I S I
, a level comparison circuit including a transistor and a second MIS transistor of an opposite conductivity type;
) a reference voltage source connected to the gate of the transistor via a second node.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The first n-channel MIS transistor M1 connected between the common input bin 1 and the third node N3 has its gate electrode also connected to the input side, and the common input bin voltage ■P
When the threshold voltage V T I of the transistor M is exceeded, that is, when Equation (5) is satisfied, the transistor Ml is turned on.

Vp > Vt+ (5) Furthermore, regarding the second p-channel MIS transistor M2 connected between the node N3 and the first node N1, the gate electrode of the transistor M2 is connected through the second node N2. When the reference voltage Vs of the reference voltage source 31 is given, the node voltage ■3 at the node N3 is higher than the node voltage ■1 at the node N, and is higher than the reference voltage Vs by the absolute value of the threshold voltage V72 of the transistor M2. is high, that is, when equation (6) holds true, transistor M2 is turned on and current flows from input common bin 1 to node N1.

vp ≧V5 +■11+I VT21...(
6) Vq>Vt...
(7) A third n-channel transistor M3 is connected to the substrate as a resistive load at the node N3. Therefore, the node voltage V! is approximately zero if the common input pin voltage VP does not satisfy Equation (6), and is determined by the voltage division characteristics depending on the on-state resistance values of transistors M and ~M3 when it satisfies Equation (6). .

Further, since the node N is connected to the input terminal of the inverter 13, the node voltage VI'3 of the thirteenth node NI3 detects the node voltage ■1 and is inverted.

FIG. 2 is an input/output voltage characteristic diagram for explaining the operation of the level comparator 301 shown in FIG. 1.

■The characteristic curve shows that when the common input pin voltage ■P is increased to set the test mode and exceeds the voltage VR that satisfies equation (8), the node voltage Vl rises and satisfies equation (9). This indicates that the line approaches the straight line L1.

VR=Vs +V't1+ l VT21...
(8) V l = V, −(V d ! + l V d 21 ) ... (9) While the common input pin voltage ■ P is maintained at the common bin input voltage maximum value VPM, the node voltage ■
1 is a slightly lower value than the value determined by the straight line L1 that satisfies Equation (9).

To release the test mode setting, set the common input pin voltage V
When p is lowered from its maximum value VPM, the nodal voltage V,
decreases according to the Vl characteristics, but eventually approaches the value of the forward voltage drop V of the pn junction diode portion existing between the transistor M3 and the fourteenth node NI4 and the transistor M3.

The node voltage V13 of the 13th node N13 also corresponds to the v1 characteristic, and the common input pin voltage ■2 satisfies the equation (8).
When the voltage drops to around R, the voltage is reversed again to the power supply voltage Vo.

That is, the V13 characteristic indicates that the node voltage V13, which is equal to the output voltage of the inverter 13, is in one of the states of the power supply voltage VD or approximately zero potential, corresponding to the (11) characteristic line.

The on-state resistance value of transistor M3 is
If the resistance values of , and M2 are selected sufficiently larger, the rise and fall of the V, characteristics and V1313 characteristics become sharp, and the V
The falling start voltage of the No. 13 characteristic can be brought closer to VR.

VR in equation (8) corresponds to the comparison voltage in the level comparator 30a.

The output voltage V13 of the comparator 30a is inverted again by the inverter 12, and its input/output voltage characteristics become equal to the characteristics of the node voltage V12 of the circuit shown in FIG. 1, thereby operating the test circuit 21 of the digital circuit 20.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and FIG. 4 is an input/output voltage characteristic diagram for explaining the operation of the circuit of FIG. 3.

The second embodiment differs from the first embodiment in that the transistor M3 is omitted.

When the analog signal voltage of the common input pin voltage VP is increased from zero to set the test mode, the node voltage ■1 becomes higher than VR in equation (8) because the ground resistance of the node N1 is high. Since the voltage rises rapidly and approaches the straight line L1 that satisfies equation (9), the node voltage VI3 as the output of the inverter 13 suddenly drops from the power supply voltage ■9 to zero potential, and the node voltage ■1□ becomes the power supply voltage V (+ The test circuit 21 is set to the operation mode.

Even if the common input pin voltage VP is lowered from its maximum value VPM, the node voltage V1 does not follow the straight line L1, but maintains the voltage VQ of equation (10), and the intersection with the straight line L2 that satisfies equation (I+) and descend along it.

V+ =VQ -VPM (VTI+ l VT21
)...(10)V=VP+VF...(
11) Here, VF is the forward voltage drop of the pn junction diode existing between 1 and the transistor M2 and the node N14.

Therefore, the inversion of the inverter 13 occurs in the middle from the voltage (1) to zero, and has a significant hysteresis characteristic with respect to the rise and fall of the common input pin voltage (2).

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

The third embodiment differs from the first embodiment in that a fifth n-channel MIS transistor M5 whose gate electrode is connected to the fourth node N4 is inserted between the transistor M1 and the node N3. That's what I'm doing.

In this embodiment, the comparison voltage V of the level comparator 30c
Its operation is the same as that of the first embodiment described above, except that Ro takes a value that satisfies equation (12), which is higher than equation (8) by the threshold voltage V75 of I-transistor M5. It is.

VRo= VS + V7I+ VT5 +l VT
21-VR+VT5'E VS + 2 VTI+ l
VT21...<12) FIGS. 6 and 7 show the reference voltage source 31 shown in FIGS. 1 to 3, respectively. 1 is a circuit diagram ′ showing a detailed circuit example.

The circuit of FIG. 6 has a seventh and ninth node between the fifth node N5 and the substrate
n-channel MIS transistors M7 and M9 are connected in series, and the power supply voltage VD applied to the fifth node N5 is set to the threshold voltage of the transistor M7 as shown in the reference voltage Vs of equation (13). ■□Descent by 7 to node N4
Output to.

Vs = Vo VT7 - (13) Here, since transistors M7 and M9 have impedances proportional to those of transistors M1 and M3 in FIG. 1, respectively, the respective threshold voltages of transistors M+ and M7 are V 7 H and V77 are almost equal, and the comparison voltage VFI when this reference voltage source 31a is connected to the node N2 in FIG. 1 is obtained by substituting equation (13) into equation (8). The formula becomes

V Ra: V o +l V T21...
(14) The circuit in Figure 7 is the transistor M7 and M9 in Figure 6.
A fourth p-channel transistor M4 corresponding to the transistor M2 in FIG.
Since the threshold voltage VT4 of 4 is lowered further than VRa of equation (14), the threshold voltage VT4 of
The comparison voltage V1b of formula 15) is obtained.

VB1. -V rLa V 74 嬌V D...
(15) In the above embodiment, the inverter 13 was used as the A/D conversion circuit, and the node voltage V13 had an inversion characteristic with the node voltage 1, but a flip-flop circuit may be used instead.

Furthermore, as an application circuit of the level comparator, an example of setting a test mode for an MIS integrated circuit has been described, or the output of the level comparator may be applied to a trigger signal of a sense amplifier of a memory circuit.

〔Effect of the invention〕

As explained above, according to the present invention, normal MIS
) By configuring the circuit using transistors, it is possible to generate a level comparison voltage with excellent temperature characteristics and high accuracy, without using specially designed MISI transistors as circuit elements, which have complicated manufacturing processes and large variations in characteristics. Easy to set up.

The effect is particularly remarkable when used in an MIS integrated circuit that has a built-in test circuit and a common manual pin for setting the test mode.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing the second embodiment of the present invention, and FIG. 4 is an input/output voltage characteristic diagram for explaining the operation of the circuit shown in FIG. Output voltage characteristic diagram,
FIG. 5 is a circuit diagram of a third embodiment of the present invention, and FIGS. 6 and 7 are a reference voltage source 31 shown in FIGS. 1 and 2, respectively.
FIG. 8 is a circuit diagram of an integrated circuit of an application example of a conventional level comparator. FIG. 9 is an input/output voltage characteristic diagram for explaining the operation of the circuit in FIG. 10 and 11 are cross-sectional views of the chip of the n-channel MIS transistor M12 shown in FIG. 8, respectively. 1... Common input pin, 2... Silicon substrate, 3a.
...Drain region, 3b...Source region, 4.5...
- Insulating film, 6... Gate electrode, 7, 8... Channel region, 11... Comparison circuit, 12.13... Inverter, 20... Digital circuit, 21... Normal circuit,
22...Test circuit, 30.30a-30c...Level comparator, 31, 31a, 3l b---...
Reference voltage source, 32a. 32b... Comparison circuit, Ll, L2... Straight line, Ml. M3. M,,M,,M9. M,...p channel MI
S transistor, M2, M4, Ml2...n
Channel MIS transistor, N, ~N6...first~
6th node, N11 to N15... 11th to 15th node, ■1°V) H to VI3... 1st. 11th to 13th node voltages, vr,...power supply voltage, ■oH...
High level output voltage, VOt...Low level output voltage, ■
2... Common input pin voltage, VPII... Maximum common input pin voltage, V,... Rising voltage of comparison circuit 32a, V11□... N-channel Mis transistor M12
threshold voltage.

Claims (1)

[Claims] an A-D conversion circuit whose input terminal is connected to the first node; a first MIS transistor of one conductivity type connected in series between the signal input terminal and the first node; and a first MIS transistor of the opposite conductivity type. 2
A level comparator comprising: a level comparator circuit including a MIS transistor; and a reference voltage source connected to the gate of the second MIS transistor via a second node.