JPS63126937U

JPS63126937U -

Info

Publication number: JPS63126937U
Application number: JP1903287U
Authority: JP
Priority date: 1987-02-12
Filing date: 1987-02-12
Publication date: 1988-08-19

Description

【図面の簡単な説明】第１図はこの考案による演算処理装置を示す一
実施例の全体構成図、第２図、第３図はその動作
を示すタイミングチヤート、第４図はその動作を
示すフローチヤート、第５図は従来の演算処理装
置を示す全体構成図である。図において、４は誤り検出パルス信号、８はＳ
Ｒフリツプフロツプ、９は割り込みステータス信
号、１１はＡＮＤ回路、１２はＣＰＵリセツト信
号、１５は誤り検出により割り込み発生、１８は
誤り検出パルスの出力により以後の処理をするか
、ＣＰＵリセツトするかをハードウエアで分岐、
２２は割り込み終了。なお、各図中同一符号は同
一または相当部分を示す。[Brief Description of the Drawings] Fig. 1 is an overall configuration diagram of an embodiment of an arithmetic processing device according to this invention, Figs. 2 and 3 are timing charts showing its operation, and Fig. 4 is a diagram showing its operation. The flowchart in FIG. 5 is an overall configuration diagram showing a conventional arithmetic processing device. In the figure, 4 is an error detection pulse signal, 8 is S
R flip-flop, 9 is an interrupt status signal, 11 is an AND circuit, 12 is a CPU reset signal, 15 is an interrupt generated by error detection, and 18 is a hardware control that determines whether to perform subsequent processing or reset the CPU by outputting an error detection pulse. Branch at,
22 is the end of the interrupt. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A CPU (Central Processing Unit) having an address bus, a data bus, a reset input terminal, and an interrupt input terminal, a latch circuit that inputs the address bus of the CPU as an input signal, and an output signal of the latch circuit that has a trigger terminal. A 2-input 1-output selector with a select control input terminal that switches the address bus signal of the CPU and controls this switching, and a selector control circuit that inputs the data bus signal of the CPU as an input signal and can be controlled by a program. and the selector control circuit inputting the output signal of the selector control circuit to the select control terminal of the selector, a memory address input terminal, a bidirectional memory data bus, and a bidirectional check bit bus for performing error correction detection. , connects the memory circuit which inputs the output signal of the selector to the memory address input terminal, and the data bus and check bit bus of this memory circuit, and outputs the error detection pulse signal and error correction data as an output signal. Bidirectional ECC (Error C) for inputting data to be stored in the circuit.
correction code: error correction code)
An ECC circuit having a data bus, an ECC circuit in which the ECC data bus of this ECC circuit is connected to the data bus of the CPU, and an error detection pulse in which the error detection pulse signal of the ECC circuit is input to the trigger terminal of the latch circuit. signal terminal and the above CP
An SR flip-flop preset control circuit which can be controlled by a program with the signal of the data bus of U as input, and an output signal of this SR flip-flop preset control circuit are input to the Reset terminal, and the above error detection pulse signal is input. SR input to the Set terminal
A flip-flop, the SR flip-flop whose output signal is input to the interrupt input terminal of the CPU, the error detection pulse signal input to one input terminal, and the SR flip-flop whose output signal is input to the interrupt input terminal of the CPU;
The error state detected by the two-input AND circuit that inputs the flip-flop output signal to the other input terminal, the AND circuit that inputs the output signal of this AND circuit to the reset input terminal of the CPU, and the ECC circuit. An arithmetic processing device characterized by comprising memory diagnostic means for determining whether memory is temporary or permanent.