JPS63126253A - Pin grid array - Google Patents

Abstract

PURPOSE:To enable a semiconductor chip to be directly connected with pins and to decrease the size of a substrate, by burying a base in a substrate for fixing a plurality of pins so as to project from the substrate, and connecting the proximal end faces of each pin to the semiconductor chip on the substrate by means of a bonding wire. CONSTITUTION:A plurality of pins 2 are fixed by burying a base in a substrate 1 so that they are projected from the substrate 1. The proximal end faces of the pins 2 are exposed from the substrate so that the proximal end faces of the pins 2 are connected to a semiconductor chip 3 packaged on the substrate 1 by means of bonding wires. When said plurality of pins 2 are arranged in several rows along the edges of the chip 3, each pin 2 in each row is arranged such that it is not overlapped with a line connecting between a pad 4 of the chip 3 and the pin 3 to be connected to said pad by means of a bonding wire. Accordingly, the chip 3 can be connected directly with each pin 2 and thus the size of the substrate can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a molded product such as an IC backer 7.

[Back g: Branch Technique 1 Chips are mounted in semiconductor packages such as 1C in order to cope with the increase in I10 number due to higher FI and higher density of elements, and the shortening of board distance due to higher speed. A pin grid array (abbreviated as PGA) in which pins for electrical connection to the outside are provided on the back surface of a substrate has been put into practical use. This pin grid array uses the entire back surface of the board to protrude a large number of pins.
The device can be attached to the motherboard by inserting the pins into sockets, through holes, etc. provided on the device's mounting board (motherboard).

FIG. 4 shows a conventional pin grid array A in which the substrate 1 is made of #l foil-covered lath-based epoxy resin laminate, glass-based polyimide resin laminate, etc. A radial circuit 12 is provided on the surface of the substrate 1 by etching, and a pin hole 13 is drilled as a through hole in the substrate 1 at the land portion of the circuit 12, and the head of the pin 2 with a diameter of about 0.5 mm is formed. Part 14
By press-fitting the pins 2 into the pin holes 13, a large number of pins 2
A pin grid array A is created by protruding from the substrate 1 while connected to each circuit 12. In this device, a wire 20 is bonded between the semiconductor chip 3 mounted on the substrate 1 and the inner lead portion of each radial circuit 12, and the semiconductor chip 3 and each of the numerous pins 2 are connected via each circuit 12. This is to connect them electrically.

However, in this case, the semiconductor chip 3 mounted on the substrate 1
Circuit 1 is installed on board 1 to electrically connect pin 2 to
2 needs to be formed radially, which poses the problem of increasing the number of circuit formation steps.In addition, in order to form a large number of circuits 12 radially while ensuring insulation spacing, the substrate 1 is formed to have a somewhat large area. need to,
There is a problem in that there is a limit to miniaturizing the pin grid array A. Furthermore, in this one, semiconductor chip 3
bonding connection between and circuit 12 and circuit 12 and pin 2
Contact connection between semiconductor chip 3 and pin 2
are electrically connected to each other, and since three connection points are required, there is a problem in that the number of steps for connection increases and the reliability of the connection decreases.

[Object of the Invention] The present invention has been made in view of the above-mentioned points, and it is possible to electrically connect a semiconductor chip and pins without the need to form a circuit on a substrate, and to connect the semiconductor chip and the pins. It is an object of the present invention to provide a pin grid array that can increase reliability, reduce the number of connection steps, and reduce the risk of short circuits during bonding.

[Disclosure of the Invention 1 The pin grid array according to the present invention has a plurality of pins 2 whose bases are embedded and fixed in the substrate 1 and is provided to protrude from the substrate 1, and the proximal end surfaces of the pins 2 are fixed from the substrate 1. The base end surface of each pin 2 is bonded to the exposed semiconductor chip 3 mounted on the substrate 1, and the plurality of pins 2 are arranged in a plurality of rows along the green part of the semiconductor chip 3. It is characterized in that the positions of the pins 2 in each row are shifted so that the straight lines connecting each pad part 4 and each pin 2 bonded to this pad part 4 do not overlap, and the semiconductor By making it possible to directly bond the chip 3 and each pin 2, it is possible to electrically connect the semiconductor chip 3 and the pins 2 without the need to form a circuit on the substrate 1. The reliability of the connection with the pin 2 can be increased, and the number of connection steps can be reduced.In addition, the position of each pin 2 in multiple rows is staggered to reduce the risk of contact during bonding. The present invention will be described in detail below with reference to Examples.

Figures 1 and 2 (of course, not to scale) show an embodiment of the present invention, in which the substrate 1 is molded from a synthetic resin molding material by injection molding, transfer molding, etc. By insert molding the bases of the pins 2 into the substrate 1 when molding the substrate 1, a large number of pins can be formed on the substrate 1. The pins 2 can be attached so as to protrude perpendicularly from the back surface of the substrate 1.

As the synthetic resin constituting the substrate 1, thermosetting resins such as phenol, epoxy, silicone, and polyimide, and thermoplastic resins such as polyphenylene sulfide, polysal 7one, and polyethersulfone sulfone can be used.

It is preferable to use an epoxy resin in terms of its proven reliability, and the latter thermoplastic resin in terms of flexibility, mechanical strength, and heat resistance. The pin 2 is formed to have a circular cross section over the entire length in the axial direction, and a pair of circular flanges 11 are provided at the base serving as the head thereof, which protrude from the entire circumference of the pin 2.

In the above embodiment, a heat sink 17 is embedded and fixed in the substrate 1 by insert molding, and a semiconductor chip 3 such as an IC chip is mounted on the surface of this heat sink 17, which forms a part of the substrate 1. That's how it is. The heat sink 17 may be made of copper, iron, aluminum, ceramic, or the like with excellent thermal conductivity. The pins 2 are attached by inserting their bases into the substrate 1 so that their base end surfaces 2a are exposed from the surface of the substrate 1, and as shown in FIG. The pins 2 are attached to the substrate 1 in rows (two rows in the illustrated embodiment) in a staggered arrangement in which the pins 2 in the inner row and the pins 2 in the outer row are staggered. Also the second
In addition to ensuring that the proximal surfaces 2a, 2a of the pins 2 in the inner row and the pins 2 in the outer row are located in the same plane as in the embodiment shown in FIG. so that the proximal surface 2 of the pin 2 in the outer row is the proximal surface 2 of the pin 2 in the inner row.
It may be set higher than a.

In the pin grid array A formed as described above, the semiconductor chip 3 mounted on the surface of the substrate 1
The electrical connection between the pad 81s4 of the semiconductor chip 3 and the base end surface 2a of each pin 2 can be achieved by bonding the wire 20 between the pad 81s4 of the semiconductor chip 3 and the base end surface 2a of each pin 2.

Since the semiconductor chip 3 and each pin 2 are directly connected by bonding in this way, there is no need to form a circuit on the substrate 1, thus eliminating the need for a circuit formation process and reducing the area required for circuit formation. Since it is no longer necessary to secure the same on the substrate 1, it becomes possible to downsize the substrate 1, and the area of the substrate becomes 173 to 1/4 of that of the conventional one shown in Fig. vJ4. In addition, when a circuit is provided on the board 1 to electrically connect the semiconductor chip 3 and the pins 2, the circuit is multi-layered on the board in order to cope with the increase in the number of circuits due to the increase in the number of pins 2. However, the present invention does not require such a circuit, so there is no such problem. Here, by shifting the positions of each pin 2 in the inner row and each pin 2 in the outer row, each pad portion 4 of the semiconductor chip 3 and each pin 2 bonded to this pad portion 4 are separated. The connecting straight lines do not overlap, and as shown in Figure @1, the wires 20 to be bonded between each pad portion 4 of the semiconductor chip 3 and the base end surface 2a of each pin 2 overlap and come into contact, causing a short circuit. This means that the danger can be lowered (only some of the pad portions 4 and wires 20 are shown in FIG. 1).

still,! @3 If the base end surfaces 2a of the pins 2 in the outer row are made to be one step higher than the base end surfaces 2a of the pins 2 in the inner row, the pins 2 in the inner row and the outer row It is possible to reliably prevent the wires 20 applied to the pins 2 in the rows from crossing each other, and the wires 20 applied to the pins 2 in the outer row from hanging on the pins 2 in the inner row.

Moreover, the bonding between the semiconductor chip 3 and the pin 2 is
Tape carrier (Tape Out) is a flexible wiring board formed by radiating circuits on a flexible film.
Bonding can be performed all at once by connecting each circuit of the tape carrier between the pad part of the semiconductor chip and the base end surface 2a of the pin 2 by heat-sealing the tape carrier using omated bonding (TAB). You can also do this. Since each pin 2 is arranged so that the straight lines connecting each pad part 4 of the semiconductor chip 3 and each pin 2 bonded to this pad part 4 do not overlap, some bonding using a tape carrier is not possible. In particular, bonding using this tape carrier can be applied when the base end surfaces 2a of the pins 2 in the inner row and the pins 2 in the outer row are on the same plane as shown in the embodiment of FIG. It is easy if you are located.

[Effects of the Invention] As described above, the present invention provides a semiconductor device mounted on a substrate by providing a plurality of pins whose bases are embedded and fixed in a substrate and protruding from the substrate, and by exposing the base end surfaces of the pins from the substrate. Since the chip and the base end surface of each pin are connected by bonding, the semiconductor chip and each pin are directly connected, and there is no need to form a circuit on the board, eliminating the need for a circuit formation process. At the same time, there is no need to reserve area for circuit formation on the board, making it possible to downsize the board, and since the semiconductor chip and each pin are directly connected, the number of connection steps is reduced. In addition, the reliability of the connection between the semiconductor chip and the pins can be improved by reducing the number of connection points. Furthermore, the pins are arranged in multiple rows along the edge of the semiconductor chip, and the positions of the pins in each row are arranged so that the straight lines connecting each pad part of the semiconductor chip and each pin bonded to this pad part do not overlap. Since the arrangement is shifted, it is possible to reduce the risk that the bonding performed between each pad portion of the semiconductor chip and the base end surface of each pin will come into contact and cause a short circuit.

[Brief explanation of the drawing]

Fig. fjS1 is a plan view of an embodiment of the present invention, Fig. tJS2 is a sectional view of the same as above, Fig. 3 is a sectional view of the embodiment of the same pond as above, and Fig. 4 is a sectional view of a conventional example. 1 is a substrate, 2 is a pin, 3 is a semiconductor chip, and 4 is a pad portion. Agent Patent Attorney Ishi 1) Head 7 1...Substrate 2...Pin 3...Semiconductor chip 4...Pad part Fig. 1 Fig. 2 Fig. 3 Fig. 4

Claims (1)

[Claims] (1) A plurality of pins whose bases are embedded and fixed in the board are provided to protrude from the board, and the base end faces of the pins are exposed from the board, and the pad part of the semiconductor chip mounted on the board and the base end face of each pin are provided. and the plurality of pins are arranged in a plurality of rows along the edge of the semiconductor chip, and the straight lines connecting each pad part of the semiconductor chip and each pin connected to this pad part by bonding do not overlap. A pin grid array characterized in that the pins in each row are arranged in a staggered manner.