JPS63124432A - Method of forming wiring of film carrier - Google Patents
Method of forming wiring of film carrierInfo
- Publication number
- JPS63124432A JPS63124432A JP61270055A JP27005586A JPS63124432A JP S63124432 A JPS63124432 A JP S63124432A JP 61270055 A JP61270055 A JP 61270055A JP 27005586 A JP27005586 A JP 27005586A JP S63124432 A JPS63124432 A JP S63124432A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- bump
- chip
- leads
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
【発明の詳細な説明】
!上皇机且分1
本発明は、フィルムキャリアの配線の形成方法に関する
。[Detailed description of the invention]! BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming wiring on a film carrier.
従来攻伎血
近年の電子機器の薄型化の要請に応じて、種々の方法が
実施提案されている。そのうちの一つとしてTAB方式
を用いた集積回路素子(以下ICチップという)の取付
方法がある。In response to the recent demand for thinner electronic devices, various methods have been proposed. One of them is a method of mounting integrated circuit elements (hereinafter referred to as IC chips) using the TAB method.
このTAB方式は、フィルムキャリアにICチップを取
付ける場合に特に薄型化に有効なものである。TAB方
式の一つの工程例としては、バンプ形成基板の表面を導
電膜で被膜し、この導電膜をパターニング技術を通用し
てバンプ用開口を形成し、バンプ用開口にメッキ技術等
を適用してAU等からなるバンプを成長させる。そのあ
とバンプを加圧・加熱して、ポリイミドフィルム上に形
成されたCu箔製のリードに転写し、その後ICチップ
をり−Yに取り付けるようにしている。This TAB method is particularly effective in reducing the thickness of a film carrier when an IC chip is attached to the film carrier. As an example of the process of the TAB method, the surface of a bump forming substrate is coated with a conductive film, a patterning technique is used to form bump openings on this conductive film, and a plating technique is applied to the bump openings. A bump consisting of AU etc. is grown. Thereafter, the bumps are pressed and heated to be transferred to Cu foil leads formed on the polyimide film, and then the IC chip is attached to the adhesive.
■が しよ゛とするロ 占
ところで、バンプ形成基板の表面ば通常鏡面研磨によっ
て表面荒さ150Å以下の鏡面に仕上げられているので
、その表面に形成されるバンプの裏面も滑らかな状態で
形成されている。By the way, the surface of the bump forming substrate is usually polished to a mirror surface with a surface roughness of 150 Å or less, so the back surface of the bumps formed on that surface will also be smooth. ing.
一方、バンプが接合されるICチップのパッドは通常ア
ルミニュウムからできていることが多く、従ってアルミ
ニュウムの表面には薄い(数10nm)酸化膜が生成し
ている。On the other hand, the pads of IC chips to which bumps are bonded are usually made of aluminum, and therefore a thin (several tens of nanometers) oxide film is formed on the surface of the aluminum.
したがって、上記バンプを介してICチップをフィルム
キャリアのリード線に接合した場合、バンプの裏面が滑
らかである関係上、アルミニュウムの酸化膜が効果的に
除去できない傾向がある。Therefore, when an IC chip is bonded to a lead wire of a film carrier through the bump, the aluminum oxide film tends to be unable to be removed effectively because the back surface of the bump is smooth.
特に、Aj!パッド中央部付近の酸化膜が除去しにくく
、そのためAllとアルミニュウムとが合金にならない
傾向があり、その結果、Affパッドとバンプとの間の
接合の強度にばらつきが生じ、ひいては製品の性能が単
一にならない上、断線のおそれがあるという問題点があ
る。Especially Aj! The oxide film near the center of the pad is difficult to remove, and therefore All and aluminum tend not to form an alloy. As a result, the strength of the bond between the Aff pad and the bump varies, and the performance of the product may deteriorate. There is a problem that the wires do not become the same and there is a risk of wire breakage.
本発明は上記事情に鑑みて創案されたもので、AJバン
ドの表面の自然酸化膜を有効に除去することにより、前
述の接合強度の向上ひいては製品の性能の向上を図るこ
とのできるフィルムキャリアの配線形成方法を提供する
ことを目的としている。The present invention was devised in view of the above circumstances, and is a film carrier that can effectively remove the natural oxide film on the surface of the AJ band, thereby improving the aforementioned bonding strength and, in turn, improving the performance of the product. The purpose of this invention is to provide a wiring formation method.
口・占 ′ るた の
本発明は、表面に微細な凹凸を有するバンプ形成基板に
パターニング手段によりバンプを形成した後、前記バン
プを介してフィルムキャリアのリード線にICチップを
取付けるようにした。In the present invention by Ruta Kuchi, after bumps are formed on a bump-forming substrate having fine irregularities on the surface by a patterning means, an IC chip is attached to the lead wire of a film carrier via the bumps.
1且
バンプ形成基板は微細な凹凸が形成されであるので、こ
れを元にして形成したバンプの裏面側も同じ形状、即ち
、凹凸状になっている。1. Since the bump-forming substrate has fine irregularities formed thereon, the back side of the bumps formed based on this has the same shape, that is, has an irregular shape.
ICチップのAnパッドにバンプを接合する場合に、バ
ンプ裏面に形成された前記微細な凹凸は、− バッド表
面に生成している薄い酸化膜を押しのける役目を果たす
。When a bump is bonded to an An pad of an IC chip, the fine irregularities formed on the back surface of the bump serve to push away a thin oxide film formed on the surface of the bump.
実JIL例−
以下、図面を参照して本発明に係る一実施例を説明する
。Practical JIL Example - Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第1図は本発明に係るバンプ形成基板10にバンプ20
が形成されている状態の模式的断面図、第2図は第1図
の模式的なA−A線拡大断面図をそれぞれ示す。FIG. 1 shows bumps 20 on a bump-forming substrate 10 according to the present invention.
FIG. 2 is a schematic cross-sectional view showing a state in which .
バンプ形成基板10は、その表面11に0.5〜1.0
μm程度の微細な凹凸が形成されたガラス基板である。The bump forming substrate 10 has a surface 11 of 0.5 to 1.0
This is a glass substrate on which microscopic irregularities on the order of μm are formed.
このバンプ形成基板10の表面11には、約0゜1μm
のチタン白金の導電膜12が蒸着等で形成され、その導
電膜12上にメッキマスクとしてのホトレジスト13等
で所定のパターン131が形成されていて、さらにパタ
ーン131にバンプ20がメッキ等の技術でもって形成
されている。The surface 11 of this bump-forming substrate 10 has a thickness of approximately 0°1 μm.
A conductive film 12 of titanium and platinum is formed by vapor deposition or the like, and a predetermined pattern 131 is formed on the conductive film 12 using a photoresist 13 or the like as a plating mask, and bumps 20 are further formed on the pattern 131 by a technique such as plating. It is formed with
従って、このようなバンプ形成基板10を用いて形成さ
れたバンプ20の裏面21(第2図参照)もバンプ形成
基板lOの表面11の凹凸に応じて微細な凹凸が形成さ
れている。Therefore, the back surface 21 (see FIG. 2) of the bump 20 formed using such a bump forming substrate 10 also has fine irregularities corresponding to the unevenness of the front surface 11 of the bump forming substrate 10.
第3図はポリイミドフィルム30のCu箔製のリード3
1にバンプ20を取り付け、そのリード31をICチッ
プ40に配線する場合の模式的工程図を示している。Figure 3 shows Cu foil leads 3 of polyimide film 30.
1 is a schematic process diagram for attaching bumps 20 to IC chip 1 and wiring the leads 31 to IC chip 40.
パターン131に形成されたバンプ20と、ポリイミド
フィルム30のリード31とを対応させて、約300℃
でバンプ20とリード31とを圧着する(第3図(al
及び第3図(bl参照)。The bumps 20 formed on the pattern 131 and the leads 31 of the polyimide film 30 are made to correspond to each other at approximately 300°C.
The bump 20 and the lead 31 are crimped together (see Fig. 3 (al.
and FIG. 3 (see bl).
この圧着によりバンプ形成基板10のバンプ20は、リ
ード31側に転写される(第3図(C1参照)。By this pressure bonding, the bumps 20 of the bump-forming substrate 10 are transferred to the lead 31 side (see FIG. 3 (C1)).
ICチップ40のAIV、パッド41に、バンプ20が
転写されたり一ド31を圧着する(第3図fdl参照)
。The bump 20 is transferred to the AIV and pad 41 of the IC chip 40, and the pad 31 is pressed (see FIG. 3 fdl).
.
その際、バンプ20の裏面21には微細な凹凸が形成さ
れているため、Aj2パッド41表面に形成されている
厚さ数10nmの酸化膜は、裏面21の凹凸によって外
側にフローして除去される。即ち、A7!パッド41表
面の自然酸化膜がバンプ20の裏面21の凹凸によって
押しのけられるのである。At this time, since minute irregularities are formed on the back surface 21 of the bump 20, the oxide film several tens of nm thick formed on the surface of the Aj2 pad 41 flows outward due to the irregularities on the back surface 21 and is removed. Ru. That is, A7! The natural oxide film on the surface of the pad 41 is pushed away by the unevenness on the back surface 21 of the bump 20.
−発1■B1果
本発明に係るフィルムキャリアの配線形成方法によると
、バンプの裏面には微細な凹凸が形成されているため、
ICチップのAAバンドにバンプの付いたリードを圧着
接合する際に、バンプの裏面の凹凸によってAj2パッ
ド表面の酸化膜が除去され、実接合面積の増加によりI
Cチップとリードとの接合強度が増し、製品のばらつき
がなくなり、断線のおそれがない。また、バンプの底面
の凹凸の段差は約0.5〜1.0μm程度であるため、
導電膜やホトレジストのカバレイジが悪化することなく
、バンプの形状にも影響がでない。-Example 1■ B1 Results According to the method for forming wiring on a film carrier according to the present invention, fine irregularities are formed on the back surface of the bumps.
When bonding a lead with a bump to the AA band of an IC chip, the oxide film on the surface of the Aj2 pad is removed due to the unevenness on the back surface of the bump, increasing the actual bonding area and increasing the I.
The bonding strength between the C chip and the leads is increased, product variations are eliminated, and there is no risk of wire breakage. In addition, since the level difference in the unevenness on the bottom surface of the bump is about 0.5 to 1.0 μm,
Coverage of the conductive film or photoresist is not deteriorated, and the shape of the bump is not affected.
第1図は本発明に係るバンプ形成基板の模式的断面図、
第2図は第1図の模式的なl−A線拡大断面図、第3図
はポリイミドフィルムのリードにバンプを取り付け、そ
のリードにICチップを配線する場合の模式的工程図で
ある。
10・・・バンプ形成基板、11・・・ハンプ形成基板
の表面、12・・・導電膜、131 ・・・パターン
、20・・ ・バンプ、31・ ・ ・リード、40・
・ ・ICチップ。
特許出願人 ローム株式会社代理人 弁理士
大 西 孝 治
第1図
第2図
第3図(a)FIG. 1 is a schematic cross-sectional view of a bump-formed substrate according to the present invention;
FIG. 2 is a schematic enlarged cross-sectional view taken along line 1--A in FIG. 1, and FIG. 3 is a schematic process diagram for attaching bumps to leads of a polyimide film and wiring an IC chip to the leads. DESCRIPTION OF SYMBOLS 10... Bump formation board|substrate, 11... Surface of hump formation board|substrate, 12... Conductive film, 131... Pattern, 20... Bump, 31... Lead, 40...
・・IC chip. Patent Applicant ROHM Co., Ltd. Agent Patent Attorney Takaharu Ohnishi Figure 1 Figure 2 Figure 3 (a)
Claims (1)
ーニング手段によりバンプを形成した後、前記バンプを
介してフィルムキャリアのリード線にICチップを取付
けるようにしたことを特徴とするフィルムキャリアの配
線形成方法。(1) Wiring of a film carrier characterized in that after bumps are formed by patterning on a bump-forming substrate having minute irregularities on the surface, an IC chip is attached to the lead wire of the film carrier via the bumps. Formation method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61270055A JPS63124432A (en) | 1986-11-13 | 1986-11-13 | Method of forming wiring of film carrier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61270055A JPS63124432A (en) | 1986-11-13 | 1986-11-13 | Method of forming wiring of film carrier |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63124432A true JPS63124432A (en) | 1988-05-27 |
Family
ID=17480890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61270055A Pending JPS63124432A (en) | 1986-11-13 | 1986-11-13 | Method of forming wiring of film carrier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63124432A (en) |
-
1986
- 1986-11-13 JP JP61270055A patent/JPS63124432A/en active Pending
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