JPS63123151A - Common bus control system - Google Patents

Abstract

PURPOSE:To equalize the distribution of bus exclusive right signals and to pinpoint the troubled hardware of a bus request line by counting the bus exclusive right signals outputted to modules and comparing the count value with the permissible number of bus exclusive right signals per cycle, which is preset to a bus exclusive use suppression register. CONSTITUTION:If bus request signal are repeatedly transmitted from the module with high priority (2-0, for instance), a bus exclusive signal counter 4 for the module 2-0 counts them. A comparison means compares the count value of the bus exclusive signal counter 4 with the suppressing value of modules 2-0-2-n, which is preset to a bus exclusive right suppression counter 5. When they agree, the request signal from the module concerned 2-0 is suppressed during a specified period. In that period the bus exclusive right signals are given to the other modules 2-1-2-n according to priority.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a common bus control method that receives bus request signals from a plurality of modules and controls the granting of a common bus occupancy signal. By counting the signals individually and comparing them with the permissible number of bus occupancy signals per arbitrary cycle, which has been written to the bus occupancy suppression register in advance, it is possible to equalize the application of bus occupancy signals and discover hard failures in the bus request line. It made it possible to do so.

[Industrial application field]

The present invention relates to a common bus control method employed in a data processing system having a common bus to which a plurality of hardware modules are connected, and a bus occupancy control circuit that manages bus request signals from each module. More specifically, the present invention relates to a common bus control system that controls and monitors the bus request signals of each module, gives equal rights to use the common bus, and ensures data processing of each module.

[Prior art]

The bus occupancy control circuit used in the conventional common bus control method, as shown in FIG. Bus exclusive right signal sending circuit 10 that grants the right to
2. In such a configuration, a bus request signal (REQO-n) from each module is input to the bus occupancy signal sending circuit 102 via the snapshot circuit 101. Each module is assigned a priority, and these priorities are determined by the bus occupancy signal transmission circuit 102. Therefore, a bus request signal (REQO) is sent from multiple modules.
~ n) is sent, the bus occupancy signal sending circuit 102 sends the bus occupancy signal (GNTO-n) to the module with the higher priority, and this module with the higher priority occupies the common bus. It was a common bus control system.

[Problem that the invention seeks to solve]

In the conventional common bus control method, the snapshot circuit 101 takes a snapshot of the bus request signal sent from each module, and the bus occupancy signal transmission circuit 102 sends a snapshot to the module with the highest priority at that time. Since a bus occupancy signal is sent out, if a bus request signal is frequently sent out from a module with a higher priority, there is a possibility that this module with a higher priority will always occupy the common bus. That is, in such a case, a module with a low priority cannot use the common bus, and it becomes impossible to process data of this module. In addition, in the conventional common bus control method, there is no function to check the bus request signal from each module, so if a problem occurs in a module with a higher priority and the bus request signal is continuously being sent, this module It also had the disadvantage that it always occupied the common bus.

An object of the present invention is to provide a common bus control method that can equally give the right to occupy the common bus to a plurality of modules connected to the common bus.

[Means for solving problems]

FIG. 1 is a block diagram for explaining the principle of the present invention.

In order to achieve the above object, the common bus control method of the present invention includes a plurality of modules 2-0 connected to the common bus 1.
In a data processing system that manages bus request signals from the modules 2-0 to 2-n and gives a bus occupancy signal for the common bus 1 to one of the modules 2-0 to 2-n, each of the modules 2-0 to 2-n A bus occupancy signal counter 4 that counts the bus occupancy right signal every .-n, a bus occupancy signal inhibition register 5 that stores an inhibition value in advance, and a count value of the bus occupancy signal counter 4 and the bus occupancy inhibition register 5. and a comparison means 8 for comparing the counter value and the inhibit value, and when the counter value and the inhibit value match, the bus request signal of the corresponding module 2-0 to 2-n is inhibited for a predetermined period, and the bus request signal of the other module is 2-0~2-
This common bus control system is characterized in that an exclusive right signal for the common bus 1 is given to n.

As an embodiment of the comparing means, the comparing means compares the count value and the inhibiting value, and when a common bus 1 exclusive right signal is given to a predetermined module 2-0 to 2-n, that module 2- It is preferable to monitor that 0 to 2-n have dropped the bus request signal.

[Effect]

With the above configuration, when a bus request signal is repeatedly sent from a module with a high priority level (for example, 2-0), the bus occupancy signal counter 4 for the module 2-0 The bus occupancy signals issued to the bus are counted. The counter value of this bus occupancy signal counter 4 is stored in advance in the bus occupancy signal suppression counter 5 of this module 2-0.
~2-n is compared with the deterrent value for n by a comparison means,
When the two match, the corresponding module 2-0 is used for a predetermined period.
The request signal from is suppressed (masked). That is,
During suppression, even if a bus request signal is sent from the module 2-0, the module 2-0 is not given the exclusive right signal for the common bus 1, and the other modules 2-1 to 2-n A bus occupancy signal is given according to the priority order. For these modules 2-1 to 2-n, bus request signals are similarly masked using arbitrary suppression values, giving an opportunity for a bus occupancy signal to be given to a lower priority module. give.

Note that even if a module that has been given a bus occupancy signal by the above action does not drop the bus request signal due to a hardware failure, it is possible to give a lower priority module a chance to be given the bus occupancy signal. It is preferable to compare whether or not the bus request signal has been dropped with respect to the exclusive right signal so that a hardware failure can be immediately detected.

〔Example〕

An embodiment of the present invention will be described in detail below based on the drawings.

First, the configuration of a bus occupancy control circuit to which the common bus control method of the present invention is adopted will be explained. FIG. 2 shows its block diagram. The bus occupancy control circuit 3 includes a bus request signal suppression circuit 9 for controlling the input of bus request signals from modules, a snapshot circuit 6, and a bus occupancy signal transmission circuit 7 having a priority function. The bus occupancy control circuit 3 also includes a bus occupancy signal counter 4 that counts bus request signals from modules, a bus occupancy signal suppression register 5 that stores arbitrary suppression values for each module, and a bus occupancy signal counter 4 that counts bus request signals from modules. a comparator 8 (hereinafter referred to as CMP), which is a comparison means for comparing the count value of No. 4 and the suppression value;
and a flip-flop latch section 10 (hereinafter referred to as FF latch section) that stores the corresponding module when a problem occurs in the bus request line of each module. The bus request signal suppression circuit 9 constitutes an input section for the bus request signals RIEQO to RIEQOn from each module.
It has a function of suppressing (masking) the bus request signals REQO to n from the corresponding modules by the output from 0. That is, when a predetermined module is masked, even if the bus request signal REQO-n is sent from this module, the bus request signal REQO~n is not transmitted to the bus occupancy control circuit 3.
It is not entered internally. The snapshot circuit 6 has a function of applying a snapshot to the bus request signals REQO to n sent from the modules via the bus request signal suppression circuit 9. The bus occupancy signal sending circuit 7 has a function of transmitting bus occupancy signals GNTO to n to the corresponding modules based on the snapshotted bus request signal sent from the snapshot circuit 6. . Furthermore, this bus occupancy signal sending circuit 7 has a priority function, and when a bus request signal is sent from multiple modules, it sends a bus request signal to the module with the highest priority among them. Only the bus occupancy signals 0NTO to n are sent out. The bus occupancy signal GNTO~n is also sent to the bus occupancy signal counter 4 and the FF latch unit 10, and the bus occupancy signal counter 4 receives the bus occupancy signal GNTO~n sent to each module for each module. It has a counting function. In other words, the number of counters in the bus occupancy signal counter 4 is small (both the number of modules is necessary, and the number of counters in the bus occupancy signal counter 4 is small). The configuration is such that the signals REQO to n are counted for each module and sent to the CMP 8.

The bus occupancy signal inhibition register 5 has a function of storing the inhibition value of each module for the common bus in one predetermined period, that is, per arbitrary cycle, that is, the number of times the common bus can be occupied, for each module, Send the value to CMP8. The CMP 8 compares the counter value of the bus occupancy signal counter 4 and the inhibition value of the bus occupancy signal inhibition register 5 for each module, and when the counter value matches the inhibition value, it outputs data indicating that they matched for at least one cycle. (match signal), and sends this match signal to the bus request signal suppression circuit 9.

The bus request signal RBQO-n from the module whose counter value and inhibition value match is masked by this bus request signal inhibition circuit 9, and the bus occupancy right of the corresponding module is inhibited until the arbitrary cycle ends. Ru. The FF rack unit 10 has a function of detecting a malfunction in each module, and the bus occupancy signal transmission circuit 7 sends the bus occupancy signal GNTO~n to a predetermined module.
If the bus request signal REQO-n from the module does not disappear even though the bus request signal REQO-n has been sent out, this malfunction state is latched in the FF latch section 10 and sent to the bus request signal suppression circuit 9, and the corresponding module The configuration is such that a mask is applied to the bus request signal REQO-H from the bus request signal REQO-H.

Next, a more detailed circuit configuration example of the present bus occupancy control circuit will be explained based on the time charts of FIGS. 3 and 4. However, this circuit will be explained using an example in which two modules are controlled, and since each circuit is symmetrical, only the circuit for one module will be explained. Bus request signal suppression circuit 9 is CMP8
-1.8-2 output and FF latch 10-1.10-2
A three-man power AND gate 14-1, which controls the bus request signals REQ0 and REQ1 from each module, and a two-man power AND gate 1)-1 which constitutes a fault detection circuit for each module. .1)-2
, JK flip-flop 12-1.12-2 and two-man power NOR gate 13-1.1)-2. In the case of this embodiment, the bus occupancy signal counter 4 is composed of two counters 4-1 and 4-2 corresponding to the number of modules, and the bus occupancy signal suppression register 5 is also composed of two registers 5-1 and 4-2. 1.5-2.

Also, the counter values of counter 4-1, 4-2 and register 5
The CMP 8 that performs the comparison with the inhibition value of -1.5-2 is also composed of two CMPs 8-1.8-2 corresponding to the modules, and the FF lie section 10 is also composed of two CMPs 8-1.8-2 corresponding to each module. It is composed of two OFF latches 10-1.10-2 and two JK flip-flops 12-1.12-2.

Here, when the bus request signal REQO is sent from the module with the higher priority, the three-man power AND gate 1
4-1. At this time, the output of the FF latch 10-1 in the initial state is L (low level), and the output of the FF latch 10-1 and the output of the AND gate 1)-1 to which the bus request signal REQO is input are also It becomes L. The output of the JK flip-flop 12-1 for delaying the output of the AND gate 1)-1 by a clock or the like also becomes L, and the output of the NOR gate 13-1 is held at H (high level). On the other hand, since the output of CMP 8-1 also becomes H while the counter 4-1 and register 5-1 do not match, the bus request signal REQO passes through the three-man AND gate 14-1, and the bus request signal REQO passes through the three-man power AND gate 14-1, and the bus request signal REQO passes through the three-way AND gate 14-1, The signal is input to the counter 4-1 via the signal sending circuit 7, and the counter value is incremented. As shown in FIG. 4, the bus exclusive right signal sending circuit 7 receives a bus request signal R
When EQO is input, the bus occupancy signal GNTO is sent to the module that issued the bus request signal REQO.

Therefore, the module can now occupy the bus,
Drops bus request signal REQO. Here, if the inhibit value of the register 5-1 is set to 2, for example, and the bus occupancy signal is issued twice according to the priority, the count value of the counter 4-1 and the inhibit value will match. , the output of CMP8-1 is set to L, and three-man power A
ND gate 14-1 is closed and the bus request signal REQO from this module is masked. After this, even if the bus request signal REQO is sent out, it is not input internally, and the pass request signal REQI of another module with a lower priority can be accepted, thereby making it possible to equalize the bus occupancy.

Next, the bus occupancy signal G is sent from the bus occupancy signal sending circuit 7.
While NTI is being output, if it is input to the FF latch 10-2, it is latched, and the output of this FF latch 10-2 becomes H. As shown in FIG. 4, the bus request signal R
If EQI does not fall due to bus occupancy signal GNT1,
The logical product of this and the output of the OFF lunch 10-2 is taken by the AND gate 1)-2, and the result is the JK flip-flop 12-2.
and closes the three-person AND game) 14-2 via the NOR gate 13-2. In this case as well, the bus request signal REQI will no longer be accepted, but bus request signals from other modules can be accepted, and invalid bus occupancy can be avoided.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications and applications can be made in accordance with the gist of the present invention.

〔Effect of the invention〕

As is clear from the above explanation, according to the common bus control method of the present invention, the ratio of bus occupancy signals sent to modules can be set by setting the inhibition value, which is the permissible number of bus occupancy signals to be acquired, in the bus occupancy inhibition register. Therefore, it is possible to arbitrarily change the bus occupancy signal and the request signal, and at the same time, it is possible to detect a fault in the request line by monitoring the bus occupancy signal and the request signal. As a result, it is possible to equalize the ratio of bus occupancy signals sent to modules by preventing them from being uneven due to module priorities or request line failures.

Therefore, there is an effect that the data processing system can be operated safely and reliably.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the principle of the present invention, Figure 2 is a block diagram of a bus occupancy control circuit adopted in the present invention, Figure 3 is a circuit diagram showing an example of its circuit configuration, and Figure 4 is its timing diagram. FIG. 5 is a block diagram showing the principle of the prior art. In the figure, ■... Common buses 2-0 to 2-n... Module 3... Bus occupancy control circuit 4... Bus occupancy signal counter 5... Bus occupancy signal suppression register 8... Comparison means It is.

Claims (2)

[Claims] (1) Bus request signals from a plurality of modules (2-0 to 2-n) connected to the common bus (1) are managed and one module (2-0 to 2-n) is sent to the common bus (1). ), a data processing system that provides a bus occupancy signal for each of the modules (2-0 to 2-n), comprising: a bus occupancy signal counter (4) that counts the bus occupancy signal for each module (2-0 to 2-n);
Bus occupancy signal suppression register (5) that stores a suppression value in advance
and a comparison means (8) for comparing the count value of the bus occupancy signal counter (4) and the inhibition value of the bus occupancy inhibition register (5), and when the counter value and the inhibition value match, a response is made. The bus request signals of the modules (2-0 to 2-n) that are
A common bus control system characterized in that an exclusive right signal for the common bus (1) is given to the common bus (1). (2) The comparison means compares the count value and the inhibition value, and also compares the count value with the inhibition value, and
Claim 1, characterized in that when an exclusive right signal of the common bus (1) is given to the module (2-0 to 2-n), the module (2-0 to 2-n) monitors whether the bus request signal is dropped. Common bus control method described.