JPS63121547A - Lamp burnout detector - Google Patents

Lamp burnout detector

Info

Publication number
JPS63121547A
JPS63121547A JP26729186A JP26729186A JPS63121547A JP S63121547 A JPS63121547 A JP S63121547A JP 26729186 A JP26729186 A JP 26729186A JP 26729186 A JP26729186 A JP 26729186A JP S63121547 A JPS63121547 A JP S63121547A
Authority
JP
Japan
Prior art keywords
delay
capacitor
constant current
transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26729186A
Other languages
Japanese (ja)
Inventor
Shinichi Yamano
山野 真市
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP26729186A priority Critical patent/JPS63121547A/en
Publication of JPS63121547A publication Critical patent/JPS63121547A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make a switchover performable without increasing terminal numbers of an integrated circuit, by making an internal circuit so as to be switched over to concentrating delay of separating delay by only connecting a concentrating or separating condenser to a capacitor connecting terminal. CONSTITUTION:A delay circuit 31 has two types of constant current sources 61 and 71, and this constant current source 71 feeds a current larger than a current I of the source 61. A constant current I flows in a transistor T1 or a terminal 51, while a constant current 1.5I flows in a diode D1 or a comparator output A side. A delay circuit 32 is also in the same constitution, having constant current sources 62 and 72 of these currents I and 1.5I, transistor T2 and a diode D2. And, an internal circuit is made so as to be switched over to concentrating delay or separating delay by only connecting concentrating or separating capacitor C, C1 and C2 to capacitor connecting terminals 51 and 52. Therefore, a switchover can be done without increasing terminal number of an integrated circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ノイズによる誤動作防止のために断線検知か
ら出力までの間に遅延(ディレィ)時間を置くランプ断
線検出装置に関し、特に2以上の検知項目に対する分離
ディレィと集中ディレィの切替えを容易にしようとする
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lamp breakage detection device that provides a delay time between detection of a breakage and output in order to prevent malfunctions due to noise, and particularly relates to a lamp breakage detection device that provides a delay time between detection of a breakage and output. This is intended to facilitate switching between separate delay and concentrated delay for detection items.

〔従来の技術〕[Conventional technology]

自動車のランプ断線検出装置は通常ストップランプとテ
ールランプの2項目を検知対象としているが、ノイズに
よる誤動作防止のため各項目について断線検知から出力
までの間に所定の遅延時間を置いている。この遅延時間
は断線検知状態が一定時間継続することをチェックする
ためのものであるので、通常はコンデンサを定電流で充
電するタイプが採用される。但し、(all検知項目2
目目上で出力が1系統の仕様と、(bl同条件で出力が
2系統の仕様があるので、前者ではコンデンサが1個で
済む集中ディレィ方式を採用し、後者では分離ディレィ
方式を採用する。
Automobile lamp breakage detection devices usually detect two items, stop lamps and tail lights, but to prevent malfunctions due to noise, a predetermined delay time is set between detection of a breakage and output for each item. Since this delay time is used to check that the disconnection detection state continues for a certain period of time, a type that charges the capacitor with a constant current is usually used. However, (all detection item 2
There is a specification with one output system and a specification with two output systems under the same conditions, so the former uses a concentrated delay method that requires only one capacitor, and the latter uses a separated delay method. .

第3図に分離ディレィ方式と集中ディレィ方式のランプ
断線検出装置の基本構成図を示す。図中、11.12は
ランプ電流に近似した基準電圧vRを発生する基準電圧
発生部、21.22は該基準電圧vRとランプ電流を基
準抵抗(後述のRs)に流したとき発生する入力電圧と
を比較するコンパレータ、31.32はその出力信号A
、Bを処理するディレィ回路、41.42はディレィ回
路の出力を反転するインバータ、51.52はコンデン
サ接続用の外部端子である。
FIG. 3 shows the basic configurations of separate delay type and concentrated delay type lamp burnout detection devices. In the figure, 11.12 is a reference voltage generation unit that generates a reference voltage vR that approximates the lamp current, and 21.22 is an input voltage that is generated when the reference voltage vR and lamp current are passed through a reference resistor (Rs to be described later). and 31.32 is its output signal A.
, B, 41.42 is an inverter that inverts the output of the delay circuit, and 51.52 is an external terminal for connecting a capacitor.

(a)の分離ディレィ方式は2つの系統が独立している
ので、検知出力1.2は2つのディレィ回路31.32
の個々の出力として得られる。これに対しくb)の集中
ディレィ方式では1つのディレィ回路31を共用するた
め、出力は単一化される。いずれの回路方式もコンデン
サC1,C2,Cを除く部分はIC化されるが、両回路
には共通部分が多いので、実際のIC化に際しては第4
図のように両方式で共用できる構成とすることが多い。
In the separated delay method in (a), the two systems are independent, so the detection output 1.2 is generated by the two delay circuits 31 and 32.
are obtained as individual outputs of On the other hand, in the concentrated delay method b), one delay circuit 31 is shared, so that the output is unified. In both circuit systems, the parts other than capacitors C1, C2, and C are integrated into ICs, but since both circuits have many common parts, when actually integrated into ICs, the fourth
As shown in the figure, a configuration that can be shared by both types is often used.

第4図でGl、G2は切替え用のゲート、SWは切替え
スイッチ、53はスイッチ接続用の外部端子である。ス
イッチSWはオン状態で端子53を0 (アース)にし
、またオフ状態で端子53を1 (開放)にするので、
オンにすると分離ディレィ方式となり、オフにすると集
中ディレィ方式になる。外付けのコンデンサC1,C2
はこれらの方式に応じて選択的に接続される。Lは検出
対象となるランプで、そのランプ電流を基準抵抗Rsに
流してコンパレータ21の入力電圧とする。コンパレー
タ22側についても同様である。
In FIG. 4, Gl and G2 are switching gates, SW is a changeover switch, and 53 is an external terminal for connecting the switch. Switch SW sets terminal 53 to 0 (ground) when it is on, and sets terminal 53 to 1 (open) when it is off.
When turned on, it becomes a separate delay method, and when it is turned off, it becomes a concentrated delay method. External capacitors C1 and C2
are selectively connected according to these methods. L is a lamp to be detected, and the lamp current is passed through a reference resistor Rs to be used as an input voltage of the comparator 21. The same applies to the comparator 22 side.

ディレィ回路31(32も同様)は第5図のように構成
され、コンパレータ21の出力Aが0のときにトランジ
スタTがオフとなり、コンデンサCは定電流■で充電さ
れる。また、コンパレータ21の出力Aが1のときはト
ランジスタTはオンするので、コンデンサCの電荷は放
電される。コンパレータCMPはコンデンサCの電圧A
’を基準電圧Eと比較し、その大小に応じた出力を示す
The delay circuit 31 (and 32 as well) is constructed as shown in FIG. 5, and when the output A of the comparator 21 is 0, the transistor T is turned off and the capacitor C is charged with a constant current . Further, when the output A of the comparator 21 is 1, the transistor T is turned on, so that the charge in the capacitor C is discharged. Comparator CMP is the voltage A of capacitor C
' is compared with the reference voltage E, and the output is shown depending on the magnitude.

このディレィ回路31のディレィ時間はコンデンサCの
容量、定電流Iの値、基準電圧Eの値で決定される。
The delay time of this delay circuit 31 is determined by the capacitance of the capacitor C, the value of the constant current I, and the value of the reference voltage E.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、第4図の構成では切替え用の端子53が必要
であり、また論理ゲー)Gl、G2も必要であることか
らIC化するには不利である。本発明はコンデンサ接続
用の端子に集中または分離用のコンデンサを接続するだ
けで内部回路が集中ディレィまたは分離ディレィに切替
わるようにするものである。
By the way, the configuration shown in FIG. 4 requires a switching terminal 53, and also requires logic games G1 and G2, which is disadvantageous when integrated into an IC. According to the present invention, the internal circuit can be switched to a concentrated delay or a separated delay simply by connecting a concentrated or isolated capacitor to a terminal for connecting a capacitor.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明の要部を示す基本構成図で、全体の構成
は第3図(a)に準拠する。第1図はこのうちのディレ
ィ回路31.32を中心とした回路図である(コンパレ
ータCMPは図示されていない)。
FIG. 1 is a basic configuration diagram showing essential parts of the present invention, and the overall configuration is based on FIG. 3(a). FIG. 1 is a circuit diagram centered on delay circuits 31 and 32 (comparator CMP is not shown).

ディレィ回路31は2種類の定電流源61.71を有し
、定電流源71は定電流源61の電流Iより大きい電流
を供給する。ここでは1.5倍の電流1.51としであ
る。定電流■はトランジスタT+または端子51に流れ
、定電流1.5IはダイオードD1またはコンパレータ
出力A側に流れる。ディレィ回路32も同様の構成で、
62は■の定電流源、72は1.5Iの定電流源、T2
はトランジスタ、D2はダイオードである。但し、ダイ
オードDI、D2はIC化される場合、トランジスタの
コレクタ・ベース間を接続して形成され、そのベースが
トランジスタTI、T2のベースに接続されることでカ
レントミラーを構成する。
The delay circuit 31 has two types of constant current sources 61 and 71, and the constant current source 71 supplies a current larger than the current I of the constant current source 61. Here, the current is 1.51, which is 1.5 times the current. The constant current (2) flows to the transistor T+ or the terminal 51, and the constant current 1.5I flows to the diode D1 or the comparator output A side. The delay circuit 32 also has a similar configuration,
62 is a constant current source of ■, 72 is a constant current source of 1.5I, T2
is a transistor, and D2 is a diode. However, when the diodes DI and D2 are integrated into an IC, they are formed by connecting the collectors and bases of transistors, and the bases are connected to the bases of the transistors TI and T2 to form a current mirror.

〔作用〕[Effect]

第1図の構成において、実線で示すように端子51.5
2間を接続し、そこに単一のコンデンサCを接続したと
する。この場合、コンパレータ出力AがH(ハイ)、B
がL(ロー)であると、トランジスタT+がオン、T2
がオフとなるため、定電流源61.62の電流の和2I
の一部がコンデンサCに流れ、残りがトランジスタT1
に流れる。トランジスタT1に流れる電流はカレントミ
ラー効果によってダイオードD+に流れる電流1゜5I
と等しいので、コンデンサCに流れる電流は21−1.
5 I=0.51   ・・・・・・■となる。コンパ
レータ出力Aがり、BがHのときはトランジスタT2に
1.5■が流れ、コンデンサCには0.5Iが流れる。
In the configuration of FIG. 1, the terminal 51.5 is shown as a solid line.
Assume that a single capacitor C is connected thereto. In this case, comparator output A is H (high) and B
is L (low), transistor T+ is on, T2
is off, the sum of the currents of constant current sources 61 and 62 2I
A part of flows into capacitor C, and the rest flows into transistor T1.
flows to The current flowing through the transistor T1 is 1°5I, which flows through the diode D+ due to the current mirror effect.
is equal to 21-1. Therefore, the current flowing through capacitor C is 21-1.
5 I=0.51...■. When the comparator output A is high and B is H, 1.5 µ flows through the transistor T2, and 0.5 I flows through the capacitor C.

以上は検知部の一方が断線検知した場合である(コンパ
レータ出力がLで断線検知)。
The above is a case where one of the detection units detects a wire breakage (a wire breakage is detected when the comparator output is L).

次に、両検知部共に断線検知してコンパレータ出力A、
Bが共にLになると、トランジスタT I+T2が共に
オフになるので、コンデンサCに流れる電流は 1+I=21           ・・・・・・■と
なる。
Next, both detection parts detect a disconnection, and the comparator outputs A,
When both B become L, both transistors TI+T2 are turned off, so the current flowing through the capacitor C becomes 1+I=21...■.

これに対し、いずれの検知部も断線検知してない状態で
はコンパレータ出力A、Bが共にHであるから、トラン
ジスタTI、T2が共にオンし、コンデンサCには 21−2X1.5 I=−I      ・・・・・・
■なる電流が流れる。これは■■とは逆に放電状態であ
る。
On the other hand, when neither detection unit detects disconnection, comparator outputs A and B are both H, so transistors TI and T2 are both turned on, and capacitor C has 21-2X1.5 I=-I.・・・・・・
■A current flows. This is a discharge state, contrary to ■■.

■■のケースではコンデンサCが充電されるので(■の
方が充電時間が長い)、コンデンサ電圧A’(=B’)
を監視するコンパレータ(第5図のCMP)は、遅延時
間後に■とは逆レベルの検知出力を出す。これは集中デ
ィレィ方式である。
In case ■■, capacitor C is charged (charging time is longer in case ■), so capacitor voltage A' (= B')
A comparator (CMP in FIG. 5) that monitors outputs a detection output at a level opposite to ■ after a delay time. This is a concentrated delay method.

一方、第1図に破線で示すように端子51.52に個々
にコンデンサCI、C2を接続すると分離ディレィ方式
となる。この場合、コンパレータ出力AがHになるとト
ランジスタT1に1.5I流れるので、コンデンサC+
には 1−1.51 =−0,5I       ・・・・・
・■流れ(放電)、また出力AがLになるとコンデンサ
C+にはIが全て流れる(充電)。従って、このコンデ
ンサ電圧A′もコンパレータで区別できる。コンデンサ
C2についても同様である。尚、定電流源71.72の
電流は00式を負にし、■式を正にする範囲(Iより大
きく、2■より小さい)から選ばれる。例示した1、5
Iはこの中間値で、最もマージンが大きい。
On the other hand, if capacitors CI and C2 are individually connected to terminals 51 and 52 as shown by broken lines in FIG. 1, a separate delay system is obtained. In this case, when the comparator output A becomes H, 1.5I flows through the transistor T1, so the capacitor C+
is 1-1.51 = -0,5I...
・■Flow (discharge), and when output A becomes L, all I flows to capacitor C+ (charge). Therefore, this capacitor voltage A' can also be distinguished by a comparator. The same applies to capacitor C2. The currents of the constant current sources 71 and 72 are selected from a range (greater than I and smaller than 2) that makes the equation 00 negative and the equation (2) positive. Examples 1 and 5
I is this intermediate value and has the largest margin.

〔実施例〕〔Example〕

第2図は本発明の実施例を示す回路図で、第1図に対応
したものである。定電圧ダイオードZDは安定した基準
電圧を作成し、これを直列抵抗R+。
FIG. 2 is a circuit diagram showing an embodiment of the present invention, and corresponds to FIG. 1. The constant voltage diode ZD creates a stable reference voltage, which is connected to the series resistor R+.

R2に印加して定電流Iの基準値を作成する。このとき
抵抗RJをR2と等しく、抵抗R4をR2の1 / 1
.5に設定すると、トランジスタT3には電流Iが流れ
、トランジスタT4には電流1.5Iが流れる。この結
果、マルチコレクタ・トランジスタT5の各コレクタか
らは定電流Iが流れ、またマルチコレクタ・トランジス
タT6の各コレクタからは定電流1.5Iが流れる。ダ
イオードD3はトランジスタT3.Taのベース・エミ
ッタ間電圧を相殺するためのものである。
A reference value of constant current I is created by applying it to R2. At this time, the resistance RJ is equal to R2, and the resistance R4 is 1/1 of R2.
.. When set to 5, a current I flows through the transistor T3, and a current 1.5I flows through the transistor T4. As a result, a constant current I flows from each collector of the multi-collector transistor T5, and a constant current 1.5I flows from each collector of the multi-collector transistor T6. Diode D3 is connected to transistor T3. This is for canceling out the voltage between the base and emitter of Ta.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、ICの端子数を増や
すことなく、集中ディレィと分離ディレィを切替えるこ
とができる。また、IC内部で論理をとる必要がないの
で素子の増加がなく、IC設計を複雑にしない利点もあ
る。
As described above, according to the present invention, it is possible to switch between concentrated delay and separated delay without increasing the number of IC terminals. Furthermore, since there is no need to implement logic within the IC, there is no need for an increase in the number of elements, and there is an advantage that the IC design does not become complicated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の要部を示す基本構成図、第2図は本発
明の実施例を示す要部回路図、第3図はランプ断線検出
装置の基本構成図、第4図は従来のディレィ方式切替え
型ランプ断線検出装置の構成図、第5図は従来のディレ
ィ回路の構成図である。 図中、11.12は基準電圧発生器、21,22はコン
パレータ、31.32はディレィ回路、51.52は外
部端子、61.62は第1の定電流源、71.72は第
2の定電流源、TI、T2はトランジスタ、DI、D2
はダイオード、Lはランプ、Rsは基準抵抗、C,CI
、C2はコンデンサである。
Fig. 1 is a basic configuration diagram showing the main parts of the present invention, Fig. 2 is a main part circuit diagram showing an embodiment of the invention, Fig. 3 is a basic configuration diagram of a lamp breakage detection device, and Fig. 4 is a conventional configuration diagram. FIG. 5 is a block diagram of a delay method switching type lamp burnout detection device, and FIG. 5 is a block diagram of a conventional delay circuit. In the figure, 11.12 is a reference voltage generator, 21 and 22 are comparators, 31.32 is a delay circuit, 51.52 is an external terminal, 61.62 is a first constant current source, and 71.72 is a second Constant current source, TI, T2 are transistors, DI, D2
is a diode, L is a lamp, Rs is a reference resistance, C, CI
, C2 is a capacitor.

Claims (1)

【特許請求の範囲】[Claims] 複数のランプ断線検知部の出力をそれぞれ遅延させる同
数の充電型ディレイ回路と、各ディレイ回路で使用する
コンデンサを外付けする外部端子とを備えたランプ断線
検知装置において、各ディレイ回路は、該ランプ断線検
知部の出力でオン、オフするトランジスタと、該トラン
ジスタまたは該コンデンサに電流を流す第1の定電流源
と、該トランジスタと共にカレントミラー回路を構成す
るダイオードおよび第2の定電流源とを備え、前記複数
の外部端子に個々にコンデンサを接続すると分離ディレ
イ方式になり、該複数の外部端子に共通のコンデンサを
接続すると集中ディレイ方式になることを特徴とするラ
ンプ断線検知装置。
In a lamp breakage detection device that includes the same number of rechargeable delay circuits that delay the output of a plurality of lamp breakage detection sections, and an external terminal to which a capacitor used in each delay circuit is externally connected, each delay circuit is configured to A transistor that is turned on and off by the output of the disconnection detection section, a first constant current source that causes current to flow through the transistor or the capacitor, and a diode and a second constant current source that configure a current mirror circuit together with the transistor. A lamp breakage detection device characterized in that when capacitors are individually connected to the plurality of external terminals, a separate delay method is used, and when a common capacitor is connected to the plurality of external terminals, a concentrated delay method is used.
JP26729186A 1986-11-10 1986-11-10 Lamp burnout detector Pending JPS63121547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26729186A JPS63121547A (en) 1986-11-10 1986-11-10 Lamp burnout detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26729186A JPS63121547A (en) 1986-11-10 1986-11-10 Lamp burnout detector

Publications (1)

Publication Number Publication Date
JPS63121547A true JPS63121547A (en) 1988-05-25

Family

ID=17442786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26729186A Pending JPS63121547A (en) 1986-11-10 1986-11-10 Lamp burnout detector

Country Status (1)

Country Link
JP (1) JPS63121547A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012164727A1 (en) * 2011-06-02 2012-12-06 トヨタ自動車株式会社 Drive device for driving voltage-driven element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012164727A1 (en) * 2011-06-02 2012-12-06 トヨタ自動車株式会社 Drive device for driving voltage-driven element

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