JPS6311997A - Voice analyzer/synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a speech analysis and synthesis device for recording and reproducing human speech and the like.

2. Description of the Related Art A conventional speech analysis and synthesis apparatus will be explained with reference to FIG. The switch 1 is a switch that switches between the voice analysis state and the voice synthesis state, and sends a signal to the control circuit 3 so that if the switch 1 is on the a side, it will be in the voice analysis state, and if it is on the b side, it will be in the speech synthesis state. input. The switch 2 is a self-resetting switch, and when the switch 2 is pressed and a pulse is input to the control circuit 3, speech analysis or speech synthesis starts. When the switch 2 is pressed in the voice analysis state, the voice input is analyzed by the voice analysis and synthesis circuit 4, converted into a digital signal, and then sequentially stored in the RAM 5 until the memory capacity of the RAM 5 is full. However, when the memory capacity becomes full, the voice analysis operation will automatically stop. At this time, the audio will be recorded in memory. When Sui Sochi 2 is pressed in the voice synthesis state, the digital signals stored in the RAM 6 in the voice analysis state are sequentially read out and sent to the voice analysis and synthesis circuit 4.
Speech is synthesized and played back as audio output. At this time as well, the speech synthesis operation is automatically stopped after all the memory contents of the RAM 5 are read out.

Problems to be Solved by the Invention However, with such a speech analysis and synthesis device, since the remaining time during speech analysis is not known, the message to be recorded may be cut off in the middle, or the message may end too quickly. The drawbacks were that silent parts became long, and during speech synthesis, it was unclear when the message being played would end.

Means for Solving the Problems In order to solve the above problems, the speech analysis and synthesis device of the present invention includes a display circuit for displaying the remaining recording time during speech analysis and displaying the remaining playback time during speech synthesis. It is equipped with the following.

Function: Since the voice analysis and synthesis device of the present invention displays the remaining time for recording or playback, it is possible to record while watching the remaining time display when analyzing the voice, so that the recorded message may be cut off in the middle, or there may be times when there is no sound. This eliminates the inconvenience of a long message, and it becomes convenient to know when a message ends when synthesizing speech.

Embodiment Hereinafter, a speech analysis and synthesis apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the speech analysis and synthesis apparatus of the present invention.

The voice analysis operation and voice synthesis operation are the same as in the conventional example,
Omitted. The difference from the conventional example is that a remaining amount time display circuit 6 is provided. In the speech analysis and synthesis device shown in Fig. 1, before switch 2 is pressed in the speech analysis state, terminals 1 to
4 is a low level. Assuming that the recording or playback time is, for example, 16 seconds, terminal 1 will be at a high level for 4 seconds from the moment switch 2 is pressed, and transistor Tr will be at a high level.
1 is turned on, current flows through the light emitting diode D1, and it lights up. Four seconds after switch 2 is pressed, terminal 1 changes from high level to low level, and at the same time, terminal 2 changes from low level to high level.

At this time, the transistor Tτ2 is turned on, current flows through the light emitting diode D2, and the light emitting diode D2 lights up. Thereafter, it operates in the same way, so the light emitting diode D1 is activated for 0 to 4 seconds after switch 2 is pressed, and the light emitting diode D2 is activated for 4 to 8 seconds.
The light emitting diode D3 lights up for 2 seconds, and the light emitting diode D4 lights up for 4 seconds each from 12 to 16 seconds. As described above, since the light emitting diode lights up while moving every 4 seconds, the remaining recording time at the time of audio analysis is displayed. In the voice synthesis state, as in the voice analysis state, the light emitting diode lights up while moving in 4-second increments, so that the remaining playback time at the time of voice synthesis is displayed. A timing chart of the above operation is shown in FIG.

In this embodiment, the lighting of the light emitting diodes is moved one by one, but in addition, for example, all four light emitting diodes are turned on at the moment switch 2 is pressed, and then one by one is turned off every 4 seconds. There is also a method of displaying the amount of time remaining, or a method of displaying the remaining amount of time numerically using segments.

Effects of the Invention As described above, the present invention allows the remaining recording time,
During speech synthesis, the remaining playback time is displayed, so during speech analysis, you can record while watching the remaining time display, and the speaker can adjust the speaking speed depending on the length of the message you are trying to record. This is extremely useful in practice, as it allows you to know the remaining time of a recorded message when synthesizing speech.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a speech analysis and synthesis device in an embodiment of the present invention, FIG. 2 is a timing chart of a speech analysis and synthesis device in an embodiment of the invention, and FIG. 3 is a block diagram of a conventional speech analysis and synthesis device. It is a diagram. 1.2... Switch, 6... Remaining time display circuit.

Claims (1)

[Claims] A speech analysis and synthesis circuit for both speech analysis and speech synthesis; a memory for storing speech analysis data during speech analysis by the speech analysis and synthesis circuit; and a memory for reading data stored during speech synthesis; a speech analysis state and a speech synthesis state; and a control circuit that controls the speech analysis and synthesis circuit and the speech analysis state and speech synthesis state of the memory by the switch, the speech analysis and synthesis device comprising: A speech analysis and synthesis device comprising a display circuit that displays time and remaining memory time during speech synthesis.