JPS63117429A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63117429A JPS63117429A JP26427986A JP26427986A JPS63117429A JP S63117429 A JPS63117429 A JP S63117429A JP 26427986 A JP26427986 A JP 26427986A JP 26427986 A JP26427986 A JP 26427986A JP S63117429 A JPS63117429 A JP S63117429A
- Authority
- JP
- Japan
- Prior art keywords
- passivation film
- film
- semiconductor device
- wiring layer
- temperature range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 238000004544 sputter deposition Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に高い耐湿性を有する半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having high moisture resistance.
従来、この種の半導体装置は、第２図に示すように半導
体基板１上に設けられたアルミニウムを主成分とする配
線層３の表面を、常圧気相成長法によりリンを含有した
シリコン酸化膜を主成分とする第１のパッシベーション
膜４ａで覆い、更にその表面をプラズマ気相成長法によ
りシリコン窒化膜を主成分とする第２のパッシベーショ
ン膜５で覆う構成のものが多用されている。Conventionally, in this type of semiconductor device, as shown in FIG. 2, the surface of a wiring layer 3 mainly composed of aluminum provided on a semiconductor substrate 1 is coated with a silicon oxide film containing phosphorus by atmospheric pressure vapor phase growth. A structure is often used in which the first passivation film 4a is covered with a first passivation film 4a mainly composed of silicon nitride, and the surface thereof is further covered with a second passivation film 5 mainly composed of a silicon nitride film by plasma vapor deposition.
パッシベーション膜を複合膜とする理由は主として、シ
リコン窒化膜の第２のパッシベーション膜５により優れ
た耐湿性を得、かつ、一般にこの第２のパッシベーショ
ン膜５中に生ずる強い圧縮応力によるリーク電流などの
悪影響を緩和する為に、緩衝材として第１のパッシベー
ション膜４ａを挟み込む為である。The reason why the passivation film is a composite film is mainly to obtain excellent moisture resistance with the second passivation film 5 made of silicon nitride film, and to prevent leakage current due to strong compressive stress that generally occurs in the second passivation film 5. This is to sandwich the first passivation film 4a as a buffer material in order to alleviate the adverse effects.
しかるに、上述した従来の半導体装置は第１のパッシベ
ーション膜４ａが常圧気相成長法により形成されたリン
を含有したシリコン酸化膜となっているので、この第１
のパッシベーション膜４ａの内部に引張り応力が生じ、
第１及び第２のパッシベーション膜４ａ、５並びに配線
層３等の変形によりクラックが発生し、温度ストレスを
加えた後は耐湿性が低下するという欠点があった０例え
ば−６５℃及び＋１５０℃の温度ストレスを交互に約１
００回加えた場合、第２図に示すようなりラック６が配
線層３の側面に生じ、このクラック６は半導体装置表面
にも達しているなめに、外界からの水分が容易に配線層
３等に浸入し耐湿性が著しく低下する。However, in the conventional semiconductor device described above, the first passivation film 4a is a phosphorus-containing silicon oxide film formed by normal pressure vapor phase epitaxy.
Tensile stress is generated inside the passivation film 4a,
Cracks occur due to deformation of the first and second passivation films 4a and 5, the wiring layer 3, etc., and moisture resistance decreases after applying temperature stress. Alternating temperature stress approx.
00 times, a rack 6 is formed on the side surface of the wiring layer 3 as shown in FIG. moisture resistance will be significantly reduced.
本発明の目的は、強い温度ストレスを加えても優れた耐
湿性を維持することができる半導体装置を提供すること
にある。An object of the present invention is to provide a semiconductor device that can maintain excellent moisture resistance even when subjected to strong temperature stress.
本発明の半導体装置は、半導体基板上に設けられたアル
ミニウムを主成分とする配線層と、前記配線層の表面を
覆う第１のパッシベーション膜と、前記第１のパッシベ
ーション膜の表面を覆うシリコン窒化物を主成分とする
第２のパッシベーション膜とを有する半導体装置におい
て、前記第１のパッシベーション膜を特定の温度範囲で
圧縮応力を有するパッシベーション膜として構成されて
いる。The semiconductor device of the present invention includes a wiring layer mainly composed of aluminum provided on a semiconductor substrate, a first passivation film covering the surface of the wiring layer, and a silicon nitride film covering the surface of the first passivation film. In the semiconductor device, the first passivation film is configured as a passivation film having compressive stress in a specific temperature range.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of the present invention.
この実施例が第２図に示す従来の半導体装置と相違する
点は、第１のパッシベーション膜４を特定の温度範囲、
例えば、装置の規定温度範囲一６５℃〜＋１５０℃にお
いて、圧縮応力を有する材質のパッシベーション膜をし
た点にある。This embodiment differs from the conventional semiconductor device shown in FIG. 2 in that the first passivation film 4 is heated within a specific temperature range.
For example, the passivation film is made of a material that has compressive stress within the specified temperature range of -65°C to +150°C.
この温度範囲で圧縮応力を有するパッシベーション膜と
しては、第１に、減圧気相成長法によるリンを含有した
シリコン酸化膜、第２に、スパッタ成長法によるシリコ
ン酸化膜、第３に、プラズマ気相成長法によるシリコン
オキシナイトライド（ＳｉＯＮ）膜などがある。５ｉＯ
Ｎ膜は比較的弱い圧縮応力を有しており、第１のパッシ
ベーション膜４として良好である。As a passivation film having compressive stress in this temperature range, firstly, a silicon oxide film containing phosphorus produced by a low pressure vapor phase growth method, secondly a silicon oxide film produced by a sputter growth method, and thirdly a silicon oxide film produced by a plasma vapor phase growth method. There is a silicon oxynitride (SiON) film produced by a growth method. 5iO
The N film has relatively weak compressive stress and is suitable as the first passivation film 4.
以上説明したように本発明は、比較的柔い材料であるア
ルミニウムを主成分とする配線層を覆う第１のパッシベ
ーション膜を、特定の温度範囲で圧縮応力を有する材質
のパッシベーション膜とすることにより、温度ストレス
が加えられても配線層及びパッシベーション膜の変形に
よるクラックを防止することができ、優れた耐湿性を維
持することができる効果がある。As explained above, the present invention provides a first passivation film that covers a wiring layer mainly composed of aluminum, which is a relatively soft material, by using a passivation film made of a material that has compressive stress in a specific temperature range. Even if temperature stress is applied, cracks due to deformation of the wiring layer and passivation film can be prevented, and excellent moisture resistance can be maintained.
本発明は、配線材料が柔かく変形しやすい場合に効果が
大きく、アルミニウムを主成分とする配線材料を用いた
場合には特に顕著である。The present invention is highly effective when the wiring material is soft and easily deformable, and is particularly effective when a wiring material whose main component is aluminum is used.
又、本発明はパッシベーション膜の表面が水分にさらさ
れやすい、いわゆるプラスチックモールド型の場合、そ
の効果が顕著である。Further, the present invention is particularly effective in the case of a so-called plastic mold type in which the surface of the passivation film is easily exposed to moisture.
第１図は本発明の一実施例を示す断面図、第２図は従来
の半導体装置の一例を示す断面図である。
１・・・・・・パッシベーション、２・・・・・・絶縁
膜、３・・・・・・配線層、４，４ａ・・・・・・第１
のパッシベーション膜、５・・・・・・第２のパッシベ
ーション膜、６・・・・・・クラック。FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of a conventional semiconductor device. 1... Passivation, 2... Insulating film, 3... Wiring layer, 4, 4a... First
Passivation film, 5...Second passivation film, 6...Crack.
Claims (1)
配線層と、前記配線層の表面を覆う第１のパッシベーシ
ョン膜と、前記第１のパッシベーション膜の表面を覆う
シリコン窒化物を主成分とする第２のパッシベーション
膜とを有する半導体装置において、前記第１のパッシベ
ーション膜を特定の温度範囲で圧縮応力を有するパッシ
ベーション膜としたことを特徴とする半導体装置。A wiring layer mainly composed of aluminum provided on a semiconductor substrate, a first passivation film covering the surface of the wiring layer, and a first passivation film mainly composed of silicon nitride covering the surface of the first passivation film. 2. A semiconductor device having a second passivation film, wherein the first passivation film is a passivation film having compressive stress in a specific temperature range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26427986A JPS63117429A (en) | 1986-11-05 | 1986-11-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26427986A JPS63117429A (en) | 1986-11-05 | 1986-11-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63117429A true JPS63117429A (en) | 1988-05-21 |
Family
ID=17400959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26427986A Pending JPS63117429A (en) | 1986-11-05 | 1986-11-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63117429A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63228627A (en) * | 1987-03-04 | 1988-09-22 | アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド | System for manufacture of integrated circuit structure |
| US5576247A (en) * | 1992-07-31 | 1996-11-19 | Matsushita Electric Industrial Co., Ltd. | Thin layer forming method wherein hydrophobic molecular layers preventing a BPSG layer from absorbing moisture |
| US8895322B2 (en) | 2005-03-01 | 2014-11-25 | Fujitsu Semiconductor Limited | Method for making semiconductor device having ferroelectric capacitor therein |
| JP2018067634A (en) * | 2016-10-19 | 2018-04-26 | 株式会社村田製作所 | Semiconductor device and method of manufacturing the same |
-
1986
- 1986-11-05 JP JP26427986A patent/JPS63117429A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63228627A (en) * | 1987-03-04 | 1988-09-22 | アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド | System for manufacture of integrated circuit structure |
| US5576247A (en) * | 1992-07-31 | 1996-11-19 | Matsushita Electric Industrial Co., Ltd. | Thin layer forming method wherein hydrophobic molecular layers preventing a BPSG layer from absorbing moisture |
| US8895322B2 (en) | 2005-03-01 | 2014-11-25 | Fujitsu Semiconductor Limited | Method for making semiconductor device having ferroelectric capacitor therein |
| JP2018067634A (en) * | 2016-10-19 | 2018-04-26 | 株式会社村田製作所 | Semiconductor device and method of manufacturing the same |
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