JPS63114325A - Digital control agc - Google Patents

Abstract

PURPOSE:To reduce the pull-in time independently of the input level of a recep tion signal by deciding a digital signal setting the amplification factor of an equalizer sequentially from the most significant bit toward the least significant bit at the time of pulling in. CONSTITUTION:The titled AGC consists of an equalizer 1 of variable gain whose amplification factor is set by a digital signal, a peak detection circuit 2 receiving an output of the equalizer 1 and deciding the presence of a peak, and a coefficient control circuit 3 deciding sequentially a digital signal from the most significant bit toward the least significant bit in response to the result of discrimination of the presence of the peak of the peak detection circuit 2 at the start of pulling in, and supplying an output to the equalizer while being increased/decreased by the weight of the least significant bit. Thus, the time required for pull-in is decreased independently of the input level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital transmission device, and particularly to a digitally controlled AGC.

[Conventional technology]

Conventionally, this type of digitally controlled AGC has an equalizer l whose amplification factor is set by a digital signal, and the presence or absence of a peak determined from the output amplitude of this equalizer 1, as shown in FIG. peak detection circuit 2.

It consisted of an up/down counter 5 that determines the digital signal from the output of the peak detection circuit 2.

Table 1 shows the relationship between the input level X of the received signal 6, the output signal CB582B+Bo of the up/down counter 5 at that time, and the amplification factor α of the equalizer l. When is in the range l≦XO B, the digital signal is (8382B
IB□) = (0110), indicating that the amplification factor at that time is α''14.The peak detection circuit 2 calculates the difference between the input level X of the received signal 6 and the amplification factor α of the equalizer 1. When the relationship is (xXa)<1, no peak is detected, (xXa)≧
When it is 1, it is determined that a peak has been detected.

The up/down counter 5 increments the digital signal by one step when the peak detection circuit 2 determines that no peak has been detected, and decreases the digital signal by one step when the peak detection circuit 2 determines that a peak has been detected. However, the value of digital No. 13 is (03B, B, Bo) = (111
Up from 1) and (83B2B+ Bo )=
Going down from (0000) will result in an overflow, so it is not executed.

For example, the operation when the input level x=h of the received signal 6 is input is as follows. If the value of digital No. 13 when there is no signal is (8382BI BO) = (1111), the amplification factor α at this time is pressure, so (xXa) = TTx
It becomes vL. Since (xXa)≧1, the peak detection circuit 2 determines that peak detection is present, and the up/down counter 5 steps down the digital signal by one step.
Set B+B0)=(1110). Since the amplification factor at this time is d, (xXa) = y, therefore (xXa
)>1, the digital signal of the up/down counter 5 is further down-stepped by l steps in the same way as above. In this way, the peak detection judgment of the peak detection circuit 2 and the countdown of the 7-up down counter 5 are repeated, and the value of the digital signal becomes CB3 82 BI BO) = (
1000), the amplification factor α becomes a value, and (X×α)=
I get it.

When (xXa) is 1, the peak detection circuit 2 determines that there is no peak detection, so the up/down counter 5 increases the digital signal by one step.B5B2 BI
BO) = (1001). In this case, the amplification factor α
is Vh, and (xXa)≧1, so the peak detection circuit 2 determines that peak detection is present, and the up/down counter 5 steps down the digital signal by one step (83B
2 81 8G) = (1000). Therefore, in this case, the value of the digital signal of up/down counter 5 is (8382B+Bo)=(1000
) and (8382BI BO) = (1001) to follow fluctuations in the input level of the received signal, and is output as the output signal 7. The state in which the digital signal fluctuates between a certain fixed value in this way is expressed as "the pull-in is completed," and the state until the digital signal reaches a certain fixed value is expressed as "the pull-in."

FIG. 5 is a diagram showing the relationship between the amplification factor α and the number of peak detection determinations when the input level of the received signal 6 is XT"Q. From this diagram, it can be seen that eight peak detection determinations are required for pull-in. -Generally, if the number of bits of the digital signal that sets the amplification factor α of the equalizer l is n bits, the pull-in time depends on the input level of the received signal 6, and depends on whether or not peak detection is performed. It requires a pull-in time of 1 to 2n times in terms of the number of determinations.

[Problem that the invention seeks to solve]

The conventional digitally controlled AGC described above pulls in the digital signal that sets the amplification factor α of the equalizer 1 one step at a time from the highest step, so the pull-in time differs depending on the input level of the received signal, and the digital signal If the number of bits is large, it may take a long time to acquire the received signal.

(Means for Solving the Problems) The digitally controlled AGC of the present invention includes a variable gain equalizer whose amplification factor is set by a digital signal, and inputs the output of the equalizer to determine the presence or absence of a peak. a peak detection circuit,
When the pull-in starts, the digital signal is sequentially determined from the most significant bit to the least significant bit according to the determination result of the presence or absence of a peak in the peak detection circuit, and when the pull-in is completed, the digital signal is increased or decreased based on the weight of the least significant bit. It has a coefficient control circuit that outputs to the equalizer.

Therefore, the time required for pull-in can be shortened without depending on the input level of the received signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of a digitally controlled AGC according to the present invention.

In this embodiment, a coefficient control circuit 3 is used in place of the up/down counter 5 of the conventional example of the digitally controlled AGC shown in FIG.

The coefficient control circuit 3 inputs the output of the peak detection circuit 2, generates a 4-bit digital signal (8382B180) for setting the amplification factor α of the equalizer 1, and outputs it to the equalizer 1. The relationship among the 4-bit digital signal, the amplification factor α, and the input level X of the received signal 6 is defined in Table 1 as in the conventional example shown in FIG.

When there is no signal initially, the digital signal of equalizer 1 is (83B
The amplification factor α is set to the maximum as 2 81 86)=(1111). Further, the digital signal at the end of the pull-in is assumed to be (A3.82+AI+Ao). When the input of the received signal 6 starts and the peak detection circuit 2 determines that (XXα)≧1, the coefficient control circuit 3 starts pulling. The coefficient control circuit 3 controls the most significant bit of the digital signal of the equalizer 1.
Change B3 to 0 (83B2 B, Bo) = (01
11). At this time, the amplification factor α is . For example, if the input level of the received signal 6 is x=h, then (XXα
), the peak detection circuit 2 determines that there is no peak detection. Based on this determination result, the amplification factor α of equalizer 1
Since a digital signal in the direction of increasing is required, A3=
It becomes 1. Next, the coefficient control circuit 3 sets 02 of the digital signal of the equalizer 1 to 0 (8382BI BO) = (A
3011). Here, the previous determination result is entered in 83, and the peak detection determination is performed as (83B, B, Bo)=(1011). The amplification factor at this time is as follows. Therefore, (XXα) = left and (x+α
)≧1, the peak detection circuit 2 determines whether peak detection is present. Since a digital signal in the direction of lowering the amplification factor is required to determine whether peak detection is present, the result of this determination is 82-0. Next, the coefficient control circuit 3 converts the digital signal of the equalizer 1 into 8. to 0 (83B2
DI BG ) = (8, 8, 01). Since the judgment result of the Of times is entered in 8,, 8, (8382[
Peak detection is determined by setting IIBo )=(1001).

The amplification factor at this time is the child. Therefore, (XXα)
Since ≧1, the peak detection circuit 2 determines whether T peak is detected. Since it is necessary to provide a digital signal in the direction of lowering the amplification factor of the equalizer 1 by determining whether or not a peak is detected, the result of this determination results in 8=0. Next, the coefficient control circuit 3 sets 60 of the digital signal of the equalizer 1 to 0 (f13 [1211186)
= (A3 82 810).

The previous judgment results are stored in 3-81 (B3B2
Peak detection is determined by setting B+no)=(1000). The amplification factor at this time is boar, (XXα)
Since it is "t", the peak detection circuit 2 determines that no peak is detected. Based on the judgment output, the coefficient control circuit 3 increases the digital signal by one step and (83B2 81B
6) Set = (ioot). Here, the coefficient control circuit 3 determines that the pull-in is completed, switches the control mode of the digital signal, and increases or decreases the weight of the least significant bit Bo. That is, the digital signal is (83Bz at
The control takes the value of Bo) and (8382BI B6)+"1" or (83B2 81 B6)-1". At this time, the coefficient control circuit 3 converts the digital signal to (83
Since it is set to 82BI BG )=(1001), the amplification factor α becomes S. Therefore, (XXα)
Since ≧1, the T peak detection circuit 2 determines that a peak has been detected, and the coefficient control circuit 3 lowers the digital signal of the equalizer 1 by one step to make (8382BI B6 ) = (1000). In this way, the coefficient control circuit 3 converts the digital signal of the equalizer 1 into (B3 ・82 Bs Bo )=Ho
oo) and (8382BI BO) = (100f) to follow fluctuations in the input level of the received signal 6. - FIG. 3 is a diagram showing the relationship between the amplification factor α and the number of peak detection determinations when the input level x of the above-mentioned received signal is &.

From this figure, it can be seen that the pull-in is completed after four peak detection determinations, counting from the input of the received signal 6. When the digital signal for setting the amplification factor of the equalizer 1 is n bits, the pull-in is completed after n times of peak detection and determination, counted from the time of input, regardless of the amplitude of the received signal 6.

FIG. 2 is a block diagram of a second embodiment of the present invention.

In this embodiment, a comparator 4 is used in place of the peak detection circuit 2 of the first embodiment.

Comparator 4 is composed of an operational amplifier, with a peak level of 8 on the inverting input and an equalizer 1 on the non-inverting input.
The output of each is input. This embodiment has the advantage of simplifying the circuit configuration because the comparator 4 makes the determination of peak detection.

〔Effect of the invention〕

As explained above, the present invention sequentially determines the digital signal for setting the amplification factor of the equalizer from the most significant bit to the least significant bit at the time of pull-in, so that the pull-in time is adjusted to the input level of the received signal. It has the effect of being shortened without being affected.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 respectively show the digital control type A of the present invention.
Configuration diagrams of the first and second embodiments of GC, FIGS. 3 and 5
The figures show the digitally controlled AGC of the first embodiment and the conventional example (Figure 4), respectively, at an input level x = 7/16.
Figure 4 is a diagram showing the relationship between the amplification factor α and the number of peak detection judgments when the received signal 6 is input.
FIG. 2 is a configuration diagram of a conventional example of GC. DESCRIPTION OF SYMBOLS 1... Equalizer, 2... Peak detection circuit, 3... Coefficient control circuit, 4... Comparator, 6... Received signal, 7... Output signal, 8... Peak level . ! :'-7 Test Tomoe Judgment Count Judgment Number 4 Figure

Claims (1)

[Claims] A variable gain equalizer whose amplification factor is set by a digital signal; a peak detection circuit that inputs the output of the equalizer and determines the presence or absence of a peak; A coefficient is determined in order from the most significant bit to the least significant bit of the digital signal according to the determination result of the presence or absence of a peak in the circuit, and when the pull-in is completed, the coefficient is increased or decreased according to the weight of the least significant bit and output to the equalizer. Digitally controlled AGC with a control circuit.