JPS63114270A - Junction type field effect transistor - Google Patents

Abstract

PURPOSE:To make it possible to perform power amplification up to a 10 GHz band, by laminating a drain region, a gate region and a source region, providing a low-concentration or intrinsic semiconductor layer between the drain region and a gate region, and forming a channel region at a side surface crossing the laminated layers. CONSTITUTION:A first-conductivity type drain region (substrate) 1, a secondconductivity type gate region 3 and a first-conductivity type source region 5 are formed in a laminated pattern. A low-concentration or intrinsic semiconductor layer 2 is provided between the drain region 1 and the gate region 3. A channel region 7 is formed at a side surface crossing the laminated layers of the drain region 1, the low-concentration or intrinsic semiconductor layer 2, the gate region 3 and the source region 5. Because of the very short length of the gate and reductions in gate capacitance, gate resistance and source resistance, an ultimate structure, in which element characteristics are determined with the transition speed of electrons, is obtained. The distance between the gate and the drain is made long and a high output impedance state is formed so as to provide breakdown strength. Thus power amplification up to a band of several tens of GHz can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a junction field effect transistor for ultra-high-speed power amplification, particularly for use in power terms up to several tens of GHz band.

[Summary of the invention]

The present invention provides a junction field effect transistor in which a drain region, a gate region, and a source region are stacked, a low concentration or intrinsic semiconductor layer is interposed between the drain region and the gate region, and a channel region is formed on a side surface crossing the stacked layers. By forming this, it is possible to increase power up to the 10 GHz band.

[Conventional technology]

A high frequency, high power transistor of several Gllz or more has not been realized using conventional silicon transistors.

In silicon junction field effect transistors, several Gll
The production itself is difficult. Although small-signal silicon bipolar transistors of 10 GIIz or higher have been developed and commercially available as high-frequency single transistors, there are no power transistors that can compete with vacuum tubes.

This is because, in a bipolar power transistor, the base and emitter are comb-shaped to reduce base resistance and emitter roughening. However, in bipolar power transistors (when excess current flows through a part of the rhombic base), the diffusion coefficients of electrons and holes increase due to extra heat generation, and the current becomes more concentrated (positive feedback loop), so the transistor Various measures have been taken to prevent this, such as inserting a resistor into the emitter, but the formation of hot spots is the fate of bipolar power transistors.

[Problem that the invention seeks to solve]

Conventional bipolar transistor power 110s F
ET is mainly used for motor control, switching power supplies, and RF power supplies with a frequency of several 100 MHz at most with a silice structure. There are no so-called high frequency analog signal power amplification transistors. This is also a limitation of silicon transistors.

M-V group compound semiconductors not only have higher electron mobility than silicon, but also have the feature that various heterostructures can be formed. For this purpose, high electron mobility transistors (
HEMT), heterojunction bipolar transistor (
New transistors such as HBT) are being devised.

The present invention provides a junction field effect transistor as an ultra-high frequency power amplification transistor, which has not been previously available, using a compound semiconductor.

[Means for solving problems]

The junction field effect transistor according to the present invention includes a drain region (1) of a first conductivity type, a gate region (3) of a second conductivity type, and a gate region (3) of a second conductivity type.
) and a source region (5) of the first conductivity type are formed in a stacked manner, and a drain region (11) and a gate region (3) are formed in a stacked manner.
) with a low concentration or intrinsic semiconductor layer (2) interposed between them, and a channel is formed on the side surface across the stack of the drain region (1), the low concentration or intrinsic semiconductor layer (2), the gate region (3) and the source region (5). Form and configure region (7).

In this case, a drain region (1) is used as a common substrate, and a low concentration or intrinsic semiconductor layer (2), a gate region (2), and a source region (5) are formed on this common substrate, separated by an insulating layer (8).
A common gate electrode (9) connected to the gate region (3) of each region (6) and a source of each region (6) are formed. It is possible to form and configure a common source electrode (11) connected to the region (5).

Furthermore, a low concentration or intrinsic semiconductor layer (4) may be interposed between the source region (5) and the gate region (3).

[Effect]

The gate length is determined by the film thickness of the gate region (3) and becomes as short as possible. Furthermore, since the low concentration or intrinsic semiconductor layer (2) is interposed between the gate region (3) and the drain region (11), the gate capacitance is reduced.
) and the gate region (3) is short (the source resistance is small; the gate resistance is also reduced).

Therefore, the device characteristics are determined by the electron transition speed.

In addition, the gate region (
3) and the drain region (11) becomes longer, resulting in a higher breakdown voltage.

Therefore, power can be increased to several tens of GIIZ bands.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a junction field effect transistor for ultra-high-speed power amplification according to the present invention will be described below with reference to FIGS.

First, as shown in FIG. 1A, on an n''-GaAs layer substrate that will become the drain region (1), an 0i-A layer with a thickness of about 5000 layers is sequentially deposited using a 110 cVD (organic metal vapor phase epitaxy) method.
Qo, q Gao, s As layer (impurity concentration n≦101
5cm-3) (2), thickness 2 for gate region (3)
000 people 7 Impurity concentration P = 3 x 10110
P"-GaAs layer of about l9', thickness, about 500 i Al2O,4Ga6.g As layer (impurity concentration n
≦10"cod-') 14), impurity concentration n = 5 x 10 with a thickness of about 2,500 which becomes the source region (5)
An n"-GaAs layer of about 110l8' is formed. Here, the NlGaAs layers (2) and (4) can be an intrinsic semiconductor or a low concentration semiconductor of n≦1015c11-'. Next, for example, RIE (reaction The epitaxially grown layers (2) to (5) are pattern-etched by ion etching or wet etching to form a plurality of separate regions (6).Next, the entire surface is etched to a thickness that will become the channel region (7). About 1,500 people re-grow an n-GaAs layer with an impurity concentration of about n=10110l7''.

Next, as shown in FIG. 1B, a gate window is opened in the center of each area (6), and the n-G
aAs layer (7), n''-GaAs layer (5) and i
An insulating layer such as S 1NJi (81) is deposited on the entire surface in a zero-order manner in which the Af2GaAs layer (4) is selectively etched away, and a resist layer (9) is deposited thereon to planarize the surface.

Next, as shown in FIG. 1C, the n+-GaAs source region (5) is exposed in each region (6) by planarization etching by RIE. Next, open the S i NWl (8) in the center of each area (6) and
After exposing the As gate region (3), a gate bridge metal is deposited, and a gate electrode (9) is formed by a lift-off method.

Next, a SiN layer (10) with a thickness of about 2,500 layers is deposited on the entire surface, and the SiN layer (10) on the top of the gate electrode (9) is formed.
The other SiN layer (10) is etched away leaving n
The surface of the ``-GaAs source region (5) is exposed again. Wet etching is used to lighten the n''-GaAs surface (((
After etching for about 200 people, a source electrode (11
) is deposited. As a result, as shown in Fig. 1 and Fig. 2, the n''-GaAs substrate is placed in a common drain region (
As 11, on this, an iAl2GaAs layer (2), a gate region (3), an i-M GaAs1i (4) and a source are respectively separated into a plurality of regions (6).
Regions (5) are sequentially stacked, a channel region (7) is formed on one side across the stack, and a gate electrode (9) and a source electrode (11) common to each region (6) are formed. A vertical junction field effect transistor (12) for ultra-high-speed power amplification is obtained.

Figure 2 is a plan view of the first diagram, in which (13) is the source pad part, (14) is the gate pad part, and (15) is commonly connected to each gate electrode (9) to apply a signal potential to each gate. This is the lead part for giving. Further, FIGS. 3 and 4 are an enlarged sectional view taken along the line BB' and an enlarged sectional view taken along the line AA' in FIG. 2. This part is a part that supplies a signal potential to the gate. In the first drawing, the gate electrode (9) on the P+-GaAs gate region (3) is covered with SiMf (lO), but in the lead part (15) that continues with this gate electrode (9), SiN The layer (10) is selectively removed and the lead portion (
The metal evaporation step 9) is performed simultaneously with the metal evaporation of the source electrode (11).

The features of the junction field effect transistor (12) having such a structure are as follows.

The gate length is completely independent of lithography rules and is determined by the film thickness of the P''-GaAs gate region (3). In this example, the gate length is 2000, but a gate length of several hundred is also possible. The length can be made as short as possible.When the gate length is shortened, normally a current flows through the substrate directly under the channel region when the gate is closed, which is called a short channel effect, making it difficult to close the gate, but in this configuration, the channel The back side of region (7) is SiN layer (8)
Therefore, short channel effects cannot occur.

The source resistance is the source region (5) and the -gate region (3).
) are separated by only 500 thin A12GaAS layers (4), so they are non-densely small. Incidentally, the source resistance Rs is calculated as follows. σ: electrical conductivity.

σ = μ en =: mJ (cJ/v, s) X 1.6X10-'
(q) XIO” (cm-XIO=45 (A/
v, cm) = 45 (1/Ωcra) Source-gate distance = 500 people = 500X 10-
10-8 (+width of channel region 1n+m= 1O-
1(c+n).

Channel depth approximately 1000 people = 1ooox 1O−
8Ccm) = -Ω; 0.1Ω The distance between the gate region (3) and drain region (1) is 5000
It is separated by a 1Aj2GaAs layer (2) about a person thick,
The gate capacitance is not that large; as a gate capacitance,
Since the source-to-gate capacitance becomes dominant, it is best to use modern lithography rules to reduce the source-to-gate contact area. Here, the 1 .mu.m line-and-space rule is used to achieve a source-gate overlap of 0.5 .mu.m, but if the 1 .mu.m rule is used carefully, an overlap of 0.25 .mu.m is also possible. Also, i −N2 between the gate region (3) and the drain region (1)
GaAsFi (21 has the role of increasing the breakdown voltage of the power transistor of this configuration. Therefore, in order to reduce the gate capacitance and increase the breakdown voltage, the concentration of the channel region (7) is set to 10" ctm-3, and this ig%
The thickness of the QGaAs layer (2) may be approximately 2 μm.

In this configuration, the point where the speed performance is degraded is not the gate length or gate capacitance (gm/C is very large), but may be the gate resistance. So let's calculate the gate resistance.

σ = μ ep = 50 (co!/v, s) X 1.6X10-1
g(q)
A/v0cm) :; 250 (1/Ωcm) Therefore, the resistivity V(1=1/250 (Ωcm) is small. In this configuration, the gate electrode (9) and the P-N junction (i.e., the channel region (7 )) is 0.75
Since it is μl, ff1=0.75. LJm, S.
= lcj, which is smaller than the normally produced metal/semiconductor ohmic contact resistance. Therefore, the speed performance is (low resistivity of the gate ohmic electrode)
It is determined by the time it takes for electrons to travel from the source region (5) to the drain region (11).
The distance from the end of the source region (5) to the end of the drain region (1) is 1 μm when the 1-Ai2GaAs layer is 0.8 μm thick.
If m is 1,', 1/τpa= 100GIIz
That is, the power tank is operated in several IQGIIz bands. The calculation of the power term ratio that is possible with this configuration is as follows.

Channel conductance G per 1 μm in the channel
o is Go"-・q・μn-N-d x 1011017(') x 500x 10-
” (cm); 5 x 1.6 x 3 x 5 x
l0-19◆341? $2-8; 100X 1O
-5 (q/ν, s) = IOX 10-' A/v (and Z: inside the gate L: gate length q: charge N: impurity concentration μn: mobility d: effective channel thickness The current value in the non-saturation region is about half of this, so 0.5 mA can flow per 1 μm in the channel. Therefore, if linear operation is performed at 10 V between the source and drain, 0.5 mAX IOV = 5 n + W / 1 μm
becomes.

When class A operation is performed, the output output to the outside is half this, 0.25 mW/1 μm.

In Figure 2, the IR level is 5 x 50 μM and the channel length is 105 μm, so the effective 1 ms +
In order to have a 1a+m chip with a withstand voltage of several hundred volts like a vacuum tube, the concentration of the channel region (7) must be set to about 5 x 10'' to make the channel thick, and the i -Ai2GaAs layer must be several microns thick. If set, τPd becomes relatively long, but it is still sufficiently usable for transmitting tubes in the 10-odd GHz band.

In this configuration, since the channel region (7) is formed in the vertical direction, the substrate can be used as the drain region (1), and therefore it is easier to manufacture than the conventional power FBT.

According to the above configuration, the device characteristics are determined by the electron transition speed due to the extremely short gate length and the reduction of gate capacitance, gate resistance, and source resistance, and the gate-drain distance is also reduced. is made long to form a high output impedance state and provide withstand voltage. Therefore,
This makes it possible to create ultra-high frequency power transistors that were not possible using silicon transistor technology.

〔Effect of the invention〕

According to the present invention, it becomes possible to realize a power term transistor in the tens of GHz band, which was not possible with conventional silicon transistors. Therefore, the junction field effect transistor of the present invention can be applied as a substitute for a vacuum tube-based power multiplier for several tens of GIIz band communications (for example, for sanitary installations, high-power mobile radios (for transmitters), etc.).

[Brief explanation of the drawing]

1A to 1D are cross-sectional views in the order of steps showing an embodiment of a junction field effect transistor according to the present invention, FIG. 2 is a plan view of FIG. 1E, and FIG. 3 is a line BB' of FIG. 2. Enlarged sectional view on the edge line,
FIG. 4 is an enlarged sectional view taken along line AA' in FIG. 2. (11 is the drain region, (2) is i A12GaAs
layers, (3) is the gate region, (4) is the 1A12GaAs layer, (5) is the source region, (7) is the channel region, (9
) is a gate electrode, and (11) is a source electrode. February 25, 1988 Commissioner of the Patent Office Kuro 1) Akio Tono 1, Indication of the case 1988 Patent Application No. 259907 3; d
Relationship with the case of a person who makes an i-correction Patent applicant address No. 6-7-35, Tokyo Parts Illustrated Product Name (2
18) Sony Corporation Representative Director Norio Ohga 4, Agent

Claims (1)

[Claims] A drain region, a gate region, and a source region are stacked, a low concentration or intrinsic semiconductor layer is interposed between the drain region and the gate region, the drain region, the low concentration or intrinsic semiconductor layer , a junction field effect transistor having a channel region on a side surface crossing the stacked layers of a gate region and a source region.