JPS63113492A - Scroll control system - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a scroll control method suitable for use in a workstation.

(Prior Art) In recent years, display functions have become more diverse with the advancement of man-machine interfaces. Particularly on workstations, in addition to conventional character displays, vector displays such as straight line drawings, and image displays are available.

Furthermore, multi-window display and advanced functions are required.
These require control using a bitmap method.

(Problem to be Solved by the Invention) By the way, if a bitmap memory is provided and the contents are moved and scrolled word by word, the processing takes time and has a negative impact on the performance of the workstation. . This is because the drawing process to rewrite the display content takes time, and this improvement is an important factor in evaluating the performance of the workstation.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a scroll control method that uses a dual-port memory to improve drawing efficiency in scroll processing.

[Structure of the Invention] (Means and Effects for Solving the Problems) In order to achieve the above object, the present invention utilizes a RAM that a dual port memory has.
It uses a bidirectional transfer mode between the port and the serial port to speed up the scrolling process. For this purpose, in addition to using the above memory as display memory, a bit mover that specifies a rectangular area of display memory bit by bit by sequentially generating addresses and transfers it to another location, and a display memory The controller includes a timing generation circuit that generates a signal that determines the data transfer direction between the RAM port and the serial port, and determines the contents of the RAM port based on the signal output from the timing signal generation circuit and the address signal output from the bitmap mover. The configuration is such that input is input to a serial port, and then the contents of the serial port are output to a different address position of a RAM port to perform scroll processing.

This can significantly reduce the time required for scroll processing.

(Example) Hereinafter, examples of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a bit mover (BMU). The bit mover 1 is a hardware logic that specifies a rectangular area in a display memory (to be described later) bit by bit and transfers it to another display location.
(bit boundary block transf
It has a function called er). This is a plain memory and a display memory with a dual port configuration. As shown in FIG. 2, the brain memory 2 has a RAM port 21 that can be randomly accessed and a serial port 22 that can be accessed via a built-in serial access memory. 3 is a timing signal generation circuit, which controls the brain memory 2.
wAddress 5trob), CA S (Co
DI o (Dlrection I) which determines the direction of data transfer between RAM port 21 and serial port 22.
nput15output) signal. The above signals are supplied to the brain memory 2 via lines 101, 102 and 103, respectively. Note that the signal propagated via line 100 is a memory address signal (MAD) supplied from bit mover 1 to brain memory 1. 4 is a display (CRT).

FIG. 3 is a timing chart showing the operation of the embodiment of the present invention, and in the diagram, the signals labeled with the same symbols as those shown in FIG. 1 are the same as those in FIG. 1.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. As shown in FIG. 1, in the embodiment of the present invention, the brain memory 2 is constructed using 16 dual port memories 64. For comparison purposes, we will use bit mover 1 to calculate the time required to scroll the entire area of the brain memory in the mode of transfer from RAM port 21 to RAM port. Assume that the data bit width between the bit mover 1 and the plain memory 2 is 16 bits.

Assuming that it takes 2 microseconds (μS) for bit mover 1 to read the source side data and write it to the location corresponding to the destination address, the number of data transfers N is N, -18 bits x 6553B/18
The bit width is -0553fi times. Therefore, the transfer time T
is T, −(i5530×2μs−131,072 milliseconds (ms)).

Next, a method of the present invention will be described in which the bidirectional transfer function between the RAM memory port 21 and the serial port 22, which is one of the functions of the dual port memory (brain memory 2), is used to speed up scrolling. First, data in the area to be scrolled is transferred to RAM port 2.
1 and the serial port 22. Parameters are given to the bit mover 1 to sequentially move from a source row address to a destination row address. Transferring the contents of row address 122 of RAM port 21 to serial port 2
READL to 2, then R the contents of serial port 22.
The row address 0 of the AM port 21 is moved. The source and destination addresses are generated by the bit mover 1 and determined by the DI/τ which determines the data transfer direction between the RAM port 21 and the serial port 22.
The signal is output from the timing signal generation circuit 3. Here, when DI/τ is at “HIGH” level, RAM
Transferred from port 21 to serial port 22, DI/
, is at “LOW” level, the serial port 22
The data is transferred from the RAM port 21 to the RAM port 21.

Assume that it takes 2 μs to transfer data from the RAM port 21 to the serial port 22 and then to the RAM port 21 again using the method of the present invention described above. By the way, according to the embodiment of the present invention, the bit width of one data transfer is 409 bits.
Since it is B bits (256 bits x 1G), the number of transfers is N.
2 is N2-85536 bits x 16 pieces/409B
The bit width is -256 times. Therefore, the transfer time T2 is T2
= 256X 2μs -0,512 (ms).

[Effects of the Invention] When using the mode in which the brain memory is transferred from the RAM port to the serial port as in the invention, the time T1 required to scroll the entire area is conventionally 1
31 ms, it only takes 0.512 rAs. Therefore, according to the present invention, the speed will be increased by about 256 times.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the brain memory shown in FIG.
FIG. 3 is a timing chart showing the operation of the embodiment of the present invention. 1... Bit mover, 2... Brain memory, 3...
...Timing signal generation circuit, 21...RAM port, 22...Serial port. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Ratio Figure 3

Claims (1)

[Claims] A dual-configuration display memory has a serial port that can be accessed via a built-in serial access memory in addition to a randomly accessible RAM port, and the rectangular area of the display memory can be divided into bits by sequentially generating addresses. a bit mover that specifies a data transfer direction and transfers the data to another location; and a timing signal generation circuit that generates a signal that determines the direction of data transfer between the RAM port and the serial port in the display memory. The feature is that the contents of the RAM port are input to the serial port based on the output signal and the address signal output by the bit mover, and then the contents of the serial port are output to a different address position of the RAM port to perform scrolling. Scroll control method.