JPS63113368A - Measurement of semiconductor device - Google Patents

Measurement of semiconductor device

Info

Publication number
JPS63113368A
JPS63113368A JP61260431A JP26043186A JPS63113368A JP S63113368 A JPS63113368 A JP S63113368A JP 61260431 A JP61260431 A JP 61260431A JP 26043186 A JP26043186 A JP 26043186A JP S63113368 A JPS63113368 A JP S63113368A
Authority
JP
Japan
Prior art keywords
power
negative
phase input
bias voltage
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61260431A
Other languages
Japanese (ja)
Inventor
Takashi Yagi
孝志 八木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP61260431A priority Critical patent/JPS63113368A/en
Publication of JPS63113368A publication Critical patent/JPS63113368A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable inspection of power, being one of AC items, among DC items, by applying a DC positive bias voltage to a normal phase input and a DC negative bias voltage to a negative phase input sequentially to measure a pseudo-AC power. CONSTITUTION:A DC positive bias voltage with a ground potential as reference is applied to a normal phase terminal 1a to measure a DC positive voltage V1 developing at a load R. Then, a DC negative bias voltage with the ground potential as reference likewise is applied to a negative phase input terminal 1b to measure a DC negative voltage V2 developing at the load R. Then, when DC waveforms of the DC voltages V1 and V2 are combined, one cycle of an AC waveform with peak values V1 and V2 are obtained in a virtual manner. Then, V0=+ or -(P0R)<1/2> is set from a power P0 and the value V0 is compared with the values V1 and V2. This enables judgement on the propriety of a power the element needs.

Description

【発明の詳細な説明】 主1上図机且分肚 本発明は、差動入力を持つ半導体装置の交流特性の一つ
であるパワーの測定方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring power, which is one of the alternating current characteristics of a semiconductor device having differential inputs.

従来皇肢血 例えば、オーディオ用リニアパワーICでは入力から出
力までアンプが直結されているため入力段に差動増幅回
路を用いて温度変化や電源変動に対し出力に直流ドリフ
トなどの影響が現れないようにしている。
For example, in audio linear power ICs, the amplifier is directly connected from the input to the output, so a differential amplifier circuit is used in the input stage, so there is no effect of DC drift on the output due to temperature changes or power supply fluctuations. That's what I do.

上記差動入力を持つパワーリニアrcは製品として完成
後、交直、流特性を検査しており、最初に差動入力に直
流信号を印加して全電流やバイアスポイントの電圧等の
直流項目を測定し、次に差動入力に交流信号を印加して
パワー、周波数帯域、歪率等の交流項目を測定する。上
記特性検査の一具体例として交流パワーの測定を第2図
を参照し、次に示すと、図において(1)はリニアI 
C,(la)  (lb)  (lc)はそれぞれリニ
アIC(1)の正相入力、逆相入力及び出力の各端子、
(2)は正相入力端子(1a)に接続される交流信号源
、(3)はリニアIC(1)の出力段に給電する電源、
(C)は逆相入力端子(1b)に接続されるフィードバ
ック用コンデンサ、(R)は出力端子(1c)に接続さ
れる負荷である。上記構成において実際の測定にあたっ
ては図示しないが、フィードバック用コンデンサ(C)
の他、入出力用カップリングコンデンサ、バイパス用コ
ンデンサ、電源用平滑コンデンサ等をリニアIC(1)
に外付けしており、負荷(R)に定格負荷を接続すると
共に正相入力端子(1a)に定格入力の交流信号を供給
し、上記各コンデンサを充電した後、負荷(R)に現れ
る電圧(V)の測定よりパワー −(P)を持つか否かを判定する。
After the above power linear RC with differential input is completed as a product, the AC/DC and current characteristics are inspected. First, a DC signal is applied to the differential input and DC items such as the total current and bias point voltage are measured. Then, an AC signal is applied to the differential input to measure AC items such as power, frequency band, and distortion rate. As a specific example of the above characteristic test, measurement of AC power is shown in FIG. 2. In the figure, (1) is a linear I
C, (la) (lb) (lc) are the positive phase input, negative phase input and output terminals of the linear IC (1), respectively;
(2) is an AC signal source connected to the positive phase input terminal (1a), (3) is a power supply that supplies power to the output stage of the linear IC (1),
(C) is a feedback capacitor connected to the negative phase input terminal (1b), and (R) is a load connected to the output terminal (1c). Although not shown in the actual measurement in the above configuration, the feedback capacitor (C)
In addition, input/output coupling capacitors, bypass capacitors, power supply smoothing capacitors, etc. are connected to linear ICs (1).
After connecting the rated load to the load (R) and supplying the rated input AC signal to the positive phase input terminal (1a) to charge each of the above capacitors, the voltage appearing at the load (R) From the measurement of (V), it is determined whether it has power -(P).

Co   ゛   赴阻点 ところで、上述したリニアICの特性検査において直流
項目の特性検査に際しては一旦、測定器をセットすると
、項目が変わっても測定器を切り換える必要はなり、又
、フィードバック用コンデンサ等の素子に外付けされる
コンデンサも少容量で、しかも必ずしも必要でないため
検査に要する時間は比較的短い、一方、交流項目の特性
検査に際しては項目が変わる毎に測定器や負荷を切り換
えるためその都度、電源を切ったり又は下げたりしなけ
ればならず、検査に要する時間が長くなる。しかも、素
子に外付けされるコンデンサの充電時間も必要でありイ
ンデックスを下げている。
By the way, when testing the characteristics of DC items in the above-mentioned linear IC characteristic test, once the measuring device is set, there is no need to switch the measuring device even if the item changes, and it is not necessary to change the measuring device even if the item changes. The capacitors attached externally to the elements have a small capacity and are not necessarily required, so the time required for testing is relatively short.On the other hand, when testing the characteristics of AC items, the measuring equipment and load are changed each time the item changes, so the test time is relatively short. The power must be turned off or lowered, which increases the time required for inspection. Moreover, charging time is required for a capacitor externally attached to the element, which lowers the index.

m   ための 本発明は、差動入力を持つ半導体装置の交流特性を測定
するにあたり、正相入力に直流正バイアス電圧及び逆相
入力に直流負バイアス電圧を順次、印加し、出力端子に
接続した負荷に現れる正負電圧と該負荷抵抗値より疑似
交流パワーを測定して上記半導体装置が定格値以上のパ
ワーを持つか否かを判別するようにしたことを特徴とす
る。
In order to measure the AC characteristics of a semiconductor device having a differential input, the present invention sequentially applies a DC positive bias voltage to the positive phase input and a DC negative bias voltage to the negative phase input, and connects it to the output terminal. The present invention is characterized in that pseudo AC power is measured from the positive and negative voltages appearing on the load and the load resistance value to determine whether or not the semiconductor device has power greater than the rated value.

土工 差動入力を持つ半導体装置の正相入力に直流正バイアス
及び逆相入力に直流負バイアス電圧を順次、印加して疑
似的に交流パワーを測定し、交流特性の検査項目の一つ
を直流特性検査で行う。
A DC positive bias voltage is sequentially applied to the positive phase input of a semiconductor device with an earthwork differential input, and a DC negative bias voltage is applied to the negative phase input to measure pseudo AC power, and one of the inspection items for AC characteristics is Performed by characteristic test.

遺」1舛 本発明に係る半導体装置の測定方法を第1図を参照して
以下説明する。第2図と同一参照符号は同一物を示す0
図において(1)はリニアIC1(la)  (lb)
  (lc)はそれぞれリニアIC(1)の正相入力、
逆相入力及び出力の各端子、(3)はリニアIC(1)
の出力段に接続される電源、(R)は出力端子(IC)
に接続される負荷である。
1. A method for measuring a semiconductor device according to the present invention will be explained below with reference to FIG. The same reference numerals as in Figure 2 indicate the same thing.
In the figure, (1) is linear IC1 (la) (lb)
(lc) is the positive phase input of linear IC (1),
Reverse phase input and output terminals, (3) are linear ICs (1)
The power supply connected to the output stage of, (R) is the output terminal (IC)
This is the load connected to the

上記構成に基づき、まず正相入力端子(1a)に、例え
ば接地電位を基準にした直流正バイアス電圧を印加して
負荷(R)に現れる直流正電圧(■1)を測定する。次
に、逆相入力端子(1b)に同じく接地電位を基準にし
た直流負バイアス電圧を印加して負荷(R)に現れる直
流負電圧(v2)を測定する。そして、直流電圧(Vl
)(V2)の各直流波形を合成すると、疑似的に波高値
(Vl)(V2)の−周期の交流波形を得る。そこで、
パワーを(P)とすると、■−土JV正よりパワー(P
)に電圧(V)が対応するため、必要とされるパワー(
Po )よりVo−±571を設定し、Voと■1及び
■2の値を比較することによりvl>JKK及びV2<
−斤71を満たせば、素子が必要なパワー(P)を持つ
と判別でき、そうでなければ不良と判別される。又、直
流電圧(■1)(v2)がクリップするまで入力端子(
1a)(1b)に印加するバイアス電圧を上げると、実
際の出力交流波形の最大波高値を知ることができる。こ
のようにしてリニアIC(1)の特性検査の交流項目の
一つであるパワーの検査を前段階の直流項目の中で行う
ことができ、その段階で不良品を除去することができる
Based on the above configuration, first, a DC positive bias voltage based on, for example, the ground potential is applied to the positive phase input terminal (1a), and the DC positive voltage (1) appearing at the load (R) is measured. Next, a negative DC bias voltage based on the ground potential is similarly applied to the negative phase input terminal (1b), and a negative DC voltage (v2) appearing on the load (R) is measured. Then, the DC voltage (Vl
) (V2), a pseudo AC waveform of -period of the peak value (Vl) (V2) is obtained. Therefore,
If the power is (P), then the power (P) from ■-Sat JV positive
), the voltage (V) corresponds to the required power (
By setting Vo-±571 from Po) and comparing Vo with the values of ■1 and ■2, vl>JKK and V2<
- If the condition 71 is satisfied, it can be determined that the element has the necessary power (P), otherwise it is determined to be defective. In addition, the input terminal (
1a) By increasing the bias voltage applied to (1b), it is possible to know the maximum peak value of the actual output AC waveform. In this way, the power test, which is one of the AC items in the characteristic test of the linear IC (1), can be performed as part of the DC items in the previous stage, and defective products can be removed at that stage.

発皿勿洟果 本発明によれば、差動入力を持つリニアICの特性検査
において交流項目の一つであるパワーの検査を前段階の
直流項目の中で行うことができ、直ちに不良となったも
のを除去できるから、特性検査に要する時間を短縮させ
ることがテキインデックスの向上を図ることができる。
According to the present invention, power, which is one of the AC items, can be tested among the DC items in the previous stage when testing the characteristics of linear ICs with differential inputs, so that defects can be detected immediately. Since the time required for characteristic inspection can be reduced, the technical index can be improved.

【図面の簡単な説明】 第1図は本発明に係る半導体装置の測定方法を示す適用
例の回路図、第2図は従来の半導体装置の測定方法を示
す一適用例の回路図である。 (1)・−・半導体装置、   (1a)−・−正相入
力、(lb) −逆相入力、    (1c)・−・出
力端子、(R)・−・負荷。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an application example showing a semiconductor device measurement method according to the present invention, and FIG. 2 is a circuit diagram of an application example showing a conventional semiconductor device measurement method. (1) ---Semiconductor device, (1a) --- Positive phase input, (lb) --- Negative phase input, (1c) --- Output terminal, (R) --- Load.

Claims (1)

【特許請求の範囲】[Claims] (1)差動入力を持つ半導体装置の交流特性を測定する
にあたり、正相入力に直流正バイアス電圧を、逆相入力
に直流負バイアス電圧を順次、印加し、出力端子に接続
した負荷に現れる正負電圧と該負荷抵抗値より疑似交流
パワーを測定して上記半導体装置が定格値以上のパワー
を持つか否かを判別するようにしたことを特徴とする半
導体装置の測定方法。
(1) When measuring the AC characteristics of a semiconductor device with differential input, a DC positive bias voltage is sequentially applied to the positive phase input and a DC negative bias voltage is applied to the negative phase input, and the voltage appears on the load connected to the output terminal. 1. A method for measuring a semiconductor device, characterized in that pseudo AC power is measured from positive and negative voltages and the load resistance value to determine whether or not the semiconductor device has power greater than a rated value.
JP61260431A 1986-10-30 1986-10-30 Measurement of semiconductor device Pending JPS63113368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61260431A JPS63113368A (en) 1986-10-30 1986-10-30 Measurement of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61260431A JPS63113368A (en) 1986-10-30 1986-10-30 Measurement of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63113368A true JPS63113368A (en) 1988-05-18

Family

ID=17347837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61260431A Pending JPS63113368A (en) 1986-10-30 1986-10-30 Measurement of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63113368A (en)

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