JPS631126A - Time synchronizing method for data transmission system - Google Patents

Abstract

PURPOSE:To synchronize a data transmission system with respect to time without interrupting the operation of an operation processing circuit nor greatly burdening the circuit by gathering time data of a slave clock in accordance with the code transmission and reception operation of the system and performing correction with data of the time difference between the slave clock and a master clock. CONSTITUTION:A slave station transmits a time TS1 of the slave clock, which is read a preliminarily determined certain time ta before by the division of a frame of the code transmitted to a master station and is stored in a register, as data in the frame following said division. After storing a time TRO of the master clock at the time of reception completion of the frame in a register, the master station subtracts the total sum of a length tc of one frame of the code, the certain time ta, and a transmission delay time td from said time TRO to calculate a slave clock estimated time TS10. The difference between this estimated time TS10 and a time TS1 of the slave clock received as data from the slave station is transmitted to the slave station as time correction data. At the time of receiving this data, the slave station adds said difference to the time of the slave clock to correct the slave clock, thereby synchronizing the slave clock with the master clock.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a data transmission system that performs bidirectional data transmission between remote points, and synchronizes the time of clocks installed at both terminal stations via a data transmission line. This invention relates to a time synchronization method for a data transmission system.

[Conventional technology] As power system R operations become more sophisticated, there is a need to accurately record and analyze the operating times and operating sequences of protective devices and equipment at each electrical station over a wide area, and to record and analyze measurement data. When collecting data, a problem has arisen in that data from different points must be collected at the same time.

As a method to solve these problems, a clock circuit is installed in the master station and each slave station of the data transmission system, and the operation of protection devices and equipment is transmitted along with this time code, and all slave stations are clocked at a predetermined time. - A possible method is to perform a total of 81 measurements at the same time, store the measurement data in memory, and then transmit it to the master station.

What is important in this case is that the clock circuits of the master and slave stations are synchronized within a practically acceptable error range, but the time required for data transmission is far greater than the time within the above error range. In order to overcome this, a special method of synchronization is required.

The conventional time synchronization method for this type of data transmission system is
When the clock circuit of the master station reaches a predetermined time, the master station transmits a time setting signal, and the slave station receives this and sets the slave station clock circuit, taking into account the transmission delay time.

[Problem that the invention seeks to solve]

The time synchronization method of conventional data transmission systems was performed as described above, and since time synchronization is performed in real time, there is no delay in operation, and the arithmetic processing circuits of the master station and slave stations suspend other operations. However, there was a problem in that the time synchronization operation had to be carried out exclusively.

Furthermore, in a system that constantly performs cyclic data transmission, there is a problem in that the flow of data must be temporarily stopped if a time synchronization signal is to be transmitted in real time.

This invention was made to solve the above-mentioned problems, and it does not interrupt the operation or impose a large burden on the arithmetic processing unit of the data transmission system, and also maintains the flow even in the case of constant cyclic transmission. The purpose of this invention is to provide a time synchronization method for a data transmission system that can perform time synchronization between a master clock and a child clock.

[Means for solving problems]

In the time synchronization method of a data transmission system according to the first invention of this application, in response to a time check command from a master station, a slave station predetermines the time from the frame break of the code being transmitted toward the master station. The time T5° of the child clock read a certain time before and stored in the register is transmitted as data in the frame following the break, and the master station transmits the time TQ0 of the master clock at the time of completion of reception of the frame. after storing it in a register.

From this code, the length of one frame tc + the fixed time ta
Estimated time T of the child clock by subtracting the sum of ten transmission delay times td
5. . and the difference T5t between this and the time Ts of the slave clock that arrived as data from the slave station.

- Send T5□ to the slave station as time correction data.

When the slave station receives this, it changes the time of the slave clock to the difference T.
5□. -T51 is added and corrected to synchronize the child clock with the master clock.

In the time synchronization method of the data transmission system according to the second invention of this application, in response to a time check command from the master station, the slave station predetermines the timing from the frame break of the code transmitted toward the master station. The time T5□ of the child clock read and stored in a register before a certain time ta is transmitted as data in the frame following the break, and the master station transmits the time T5□ of the child clock that was read and stored in a register before a certain time ta, and the master station transmits the time T5 After the time T is stored in a register, the time Ts1 of the slave clock arrives as data from the slave station, the transmission delay time td, the time from reading the time of the slave clock to transmitting the code, ta, the length of one code frame. Child clock estimated time Tρ by adding the sum of tc. , and the difference between this and the time TRo of the master clock at the time of completion of reception of the frame is 'rr2. -'r, , 1 is sent to the slave station as time correction data, and upon receiving this, the slave station corrects the time of the slave clock by adding the difference 'rp, -Tρ1°, thereby correcting the time of the slave clock. is synchronized with the master clock.

[Effect]

No. 1 of this application. In the time synchronization method of the data transmission system according to the second invention, as described above, since the slave clock is corrected using the data of the time difference between the master clock and the slave clock, the correction operation does not need to be performed immediately, but can be carried out between other operations. can be done.

In addition, reading the time between the master clock and slave clock to obtain time difference data is done in conjunction with the code transmission and reception that is always taking place, and is stored in a register, so both the master station and slave stations can perform calculations. The burden on the processing device is light, and there is no need to stop the flow of data transmission even in the case of a system that performs cyclic data transmission.

〔Example〕

FIG. 1 shows a time synchronization method for a data transmission system according to the present invention, which is performed by a supervisory control and control system.
Data Acquisition (Supervisory)
Control And Data Acquisi
tion.

FIG. 2 is a diagram showing an example of time synchronization between a master clock installed in a master station of a system (hereinafter referred to as 5CADA) and slave clocks installed in each slave station. In the figure, 0 is 5CA
The master station of the DA system, 1, 2°, . . . are slave stations. At the master station O, the GP is connected to each slave station 1, 2 .・・・・・・
・The display board and CD displaying the status of each slave station 1, 2.・・・
A control console is used to issue control commands to..., TW is a typewriter for recording operations and data, CPU is an arithmetic processing circuit, DO is an output circuit, and DI. is the input circuit, TC
is the typewriter control circuit, MC is the master clock, RG, 1. R
G, oh... is a register, S e, t Sow
s... is a code transmission circuit, Ro engineering.

R02, ...... is a code receiving circuit, M6zHMo2
g... is a modulation circuit, D01. D...
... is a demodulation circuit.

In the slave stations 1 and 2, CPU, CPU2 are arithmetic processing circuits, Dl and D are demodulation circuits, and Ml and M are demodulation circuits.

is a modulation circuit, R1 and R2 are code receiving circuits, S + SZ are code transmitting circuits, DO□, Do are output circuits, and DI.

DI is the input circuit, LCl, LC2 is the slave clock, RG,
.

RG2 is a register.

LxD+Liu+LzDy L2u""" is a data transmission path connecting the master station O and each slave station 1, 2, . . . .

Next, the operation shown in FIG. 1 will be explained using FIG. 2, which shows a time chart of codes transmitted and received between the master station O and the slave station 1.

First, a case will be described in which normal remote monitoring control and operation recording are performed.

In FIG. 1, the arithmetic processing circuit CPU1 of the slave station 1 scans the state of monitored contacts (auxiliary contacts of protective relays, circuit breakers, etc.) input to the input circuit DI, and stores the state. If there is a change in the state of the input contact, the address number and new state of the contact are passed to the code transmission circuit S1. Code transmission circuit S.

is constantly transmitting a code toward the master station O, and when it receives the address and disconnected state data of the state change contact from the arithmetic processing circuit CPU, it transmits the code next to the code it is currently transmitting. It is passed to the modulation circuit M0 to be put on a frame and sent to the master station O. An example of the code transmitted by the code transmitting circuit S1 is shown in S□ in FIG. In FIG. 2, D is each frame of the code.

F is a flag indicating a break between frames 40.

The pattern of flag F is fixed, but frame D, including its length, changes depending on the content to be sent. In addition to the data to be transmitted, the contents usually include a control part and a code check part to ensure transmission and reception. An example of the code format is High-Level Data Link Control (High-Level).
el Data Link Control, hereinafter H
There is a version of Prosuigea (called DLC).

Returning to FIG. 1, the modulation circuit M1 is a code transmission circuit S.

The code received from
shift keying (hereinafter referred to as FSX) signal and transmits it to the master station O via the signal transmission path L 1 u.

In the master station 0, the demodulation circuit Do receives this, demodulates it into a DC pulse, and passes it to the code reception circuit Rn1.

The code reaching the code receiving circuit R0□ is Rol in FIG.
is similar to the transmission code S1, but is delayed by the transmission delay time td.

The arithmetic processing circuit CPU of the master station O reads the received contents through periodic scanning or an interrupt signal from the code receiving circuit R0, and updates the contents of its own storage device when state change data arrives. At the same time, the display on the display panel GP is changed via the output circuit Doo. In addition, the typewriter TV records state changes via the typewriter control circuit TC.

The arithmetic processing circuit CPU of the master station O is an input circuit DI.

The input from the control console CD is also scanned through the slave station 1.
When there is a command to select or control a device, the corresponding device address and the state to be controlled (on/off, etc.) are encoded and sent to the code transmission circuit Set. Code transmission circuit S. , transmits the code shown in the SOI in FIG. 2, and transmits the code shown in the SOI in FIG. The arithmetic processing circuit CPU1 reads the received contents through periodic scanning or an interrupt signal from the code receiving circuit R1, performs a code check and decoding, and gives a control command to the assigned device via the output circuit Do□. .

The above operation is exactly the same for the slave station 2, so a description thereof will be omitted. Moreover, the same additional configuration can be applied to slave stations 3 and below (not shown), so that they can perform exactly the same operation.

The above is the normal operation of remote monitoring control and operation recording, but when the operation is recorded at the master station O, in the above normal operation, each slave station 1, 2... However, since the data of the time when the state change occurred is not received, there is no other way than to record the time of the master clock MC in the order confirmed by the arithmetic processing circuit CPU of the master station 0. In cases where the operation of protection devices and equipment is much faster than the time required for code transmission of data transmission equipment, such as in power systems, it is no longer possible to accurately determine the order of operation by the time the data reaches master station 0. .

In order to solve this problem, each slave station 1, 2. ...... are provided with child clocks LC□,, LC,, ..., synchronized with the master clock MC, and when a state change occurs, child clocks LC1, LC,... , . . . are also transmitted to the master station O. That is, when there is a change in the state of the contact input to the input circuit DI of the slave station 1 described above, the arithmetic processing circuit CPU will input the address number of the corresponding contact,
If the disconnected state and the time of the slave clock LC are transmitted to the master station 0, the arithmetic processing circuit CPU of the master station 0 temporarily stores this in its own storage device, and also collects data from the slave stations at certain times. By arranging the information in the order of added times and printing it out on the typewriter TV via the typewriter control circuit TC, the operator can know the correct operation time and sequence.

In this case, the master clock MC of the master station O and each slave station 1, 2°...
It is necessary that the child clocks LC, LC2, .

The arithmetic processing circuit CPU0 of the master station 0 checks each child clock LC,, LC once every certain period of time (1 hour to 1 day depending on the accuracy of the child clock).
, . ITS1121・・・・・・
Each slave station 1, 2 . Emit to...

To explain about the slave station 1, first, as a normal operation, the code transmitting circuit S gives a signal to the register RG a predetermined time ta before the start of code frame transmission, and the register RG1 outputs a signal to the slave station at the time when this signal arrives. The operation of reading the time of the clock LC□ and storing it is repeated. When the arithmetic processing circuit CPU of the master station 0 issues a time check command, the code transmission circuit S. 1 is a modulation circuit M. 1. Transmission line LID
, and is transmitted to the code receiving circuit R□ of the slave station 1 via the demodulating circuit D1.

This operation is shown as D(TIQ) in the time chart diagram of FIG.

When the code receiving circuit R1 receives the time check command D (TIQ), the arithmetic processing circuit CPU□ of the slave station 1 places the data stored in the register RG on the next code frame, but the data in the register RG is As shown in the upper part of 81 in Fig. 2, contains the time of the child clock LC□ which is ta before the next frame (in this example, the time when the transmission of the previous frame is completed), and if this is T5□, then In the next frame D (TAS), this r5i is used as the time data of the child clock LC in the code transmission circuit S1, the modulation circuit M0. Transmission line Ltu, demodulation circuit D
01 to the code receiving circuit R111 of master station 0.

The code arriving at the code receiving circuit R01 is Ro in FIG.
This is the same as the transmission code S1, but delayed by the transmission delay time td. When the code receiving circuit R6 completes receiving the frame carrying the time data of the child clock LC1, it reads the current time TRo of the master clock MC into the register RG,1 and stores it.

The arithmetic processing circuit CPU reads the time data T9° entered in the register RG, □, and calculates the length of one code frame known in advance tc + the time ta from the time reading of the slave clock to the sending of the code described above. The child clock estimated time T5 is obtained by subtracting the total transmission delay time td. and slave station 1.
The difference T5□ with the child clock time Ts1 that arrived with the frame D(TAS). If -Ts□ is taken, this becomes the time difference between the master clock O and the slave clock 1, so it is stored in its own storage device.

Next, the arithmetic processing circuit CPU sends the code transmission circuit S and modulation circuit M using the time difference as slave clock correction data. The signal is transmitted to the code receiving circuit R1 of the slave station 1 via a transmission path L x D and a demodulation circuit. A time chart of this operation is shown by D (TAJ) in FIG.

When the code receiving circuit R□ receives the time correction data D (TAJ), the arithmetic processing circuit CPU of the slave station 1 changes the slave clock LC1.
The time of the child time LC is read out, the time correction data is added to it (including the sign), and the time of the child time LC is set to that time.

As a result, the time of the child clock LC1 is synchronized with the time of the master clock MC.

The time synchronization can be performed for the slave clocks LC, .

Contrary to the above, the time correction data is sent to the arithmetic processing circuit CPU of the master station 0 based on the time Ts of the slave clock LC1 that has arrived from the slave station 1.
The child clock estimated time 'rp1. The difference TQt between the time TOa of the master clock 0 and the time TOa of the master clock 0 at the time of completion of reception of the code frame that arrived with the child clock time T51. - It can also be obtained as TQa.

Since the time synchronization method according to the present invention can be applied to a data transmission system that constantly transmits codes, that system is also listed in the embodiment, but other encoding systems, such as constantly transmitting codes, are not applicable. Polling from the master station (Po
It goes without saying that the present invention can also be applied to a system in which each slave station transmits a code in accordance with the timing (Illing).

Also in the configuration of the embodiment, for example, the register RG of the master station O
, 1. If RGa, . Of course, various configurations can be made, such as by sequentially using shared registers.

In addition, the transmission delay time td between the master station and each slave station is determined by the loopback test of the modulation/demodulation circuit when the data transmission system is installed.
For example, in FIG. 1, the modulation circuit M of the master station 0. A demodulation circuit. The modulation circuit M1 and the demodulation circuit D of the slave station 1 and the slave station 1 are separated from the internal circuit, and the output of the demodulation circuit D□ is connected to the modulation circuit M□ of the slave station 1, and the modulation circuit M of the master station O is connected. The change in the input sign of i is the demodulation circuit. Measure the time delay until it appears on the output of 1, divide this by 2, etc., and then
It is sufficient to store it as data in the storage device of the arithmetic processing circuit CPU0.

In addition, the time adjustment operation is performed every time when all digits of the time (hours, minutes, seconds,
milliseconds).
The time of the child clock and its correction data are corrected to the second when the device is started or at long intervals (or the time of the child clock is set by transmitting the absolute time), and the time is corrected to the millisecond once every hour. It is possible to reduce the bit length of

〔Effect of the invention〕

As mentioned above, the first part of this application. According to the second invention, the time data of the slave clock is collected in accordance with the code transmission/reception operation of the data transmission system, and the adjustment operation is not based on absolute time but is performed using data on the time difference with the master clock. Therefore, there is an effect that there is no interruption of operation or a large burden on the arithmetic processing circuit of the data transmission system, and even in the case of constant cyclic transmission, the time cycle can be performed while maintaining the flow.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the time synchronization method of the data transmission system according to the present invention in a 5CADA system, and FIG. 2 shows the code transmitted and received between the master station 0 and slave station 1 in FIG. It is an explanatory diagram showing an example. 0 is the master station, 1, 2. ...... is a slave station, CPU is an arithmetic processing circuit, MC is a master clock, RG, , RG, ,, -.
... is register + Snl + 5oal...
・ is a code transmitting circuit, R, 1, Ro, . . . is a code receiving circuit, CPU. CPU U2. ...... is an arithmetic processing circuit, LC□, L
C2゜... is a child clock, RGl, RG2. ...
. . . are registers, R1, R2, . . . are code receiving circuits, S□, S2 . ... is a code transmitting circuit, L
icy Lzut Lift Lzut """ is a transmission line connecting master station 0 and slave stations 1, 2, etc. Patent applicant Mitsubishi Electric Corporation O -- 〇's γ procedure amendment (voluntary)

Claims (2)

[Claims] (1) In a time synchronization method for a data transmission system that performs bidirectional data transmission between a master station and a slave station, a slave clock installed in the slave station is time-synchronized with a master clock installed in the master station. When synchronizing, the slave station responds to a slave clock time check command from the master station and starts at a predetermined time (t) from the frame break of the code being transmitted to the master station.
a) The time of the child clock previously read and stored in the register (
T_S_1) is transmitted as data in the frame following the break, and the master station stores the time (T_R_0) of the master clock at the time of completion of reception of the frame in a register, and from now on, one code frame is transmitted. length (tc) +
Calculate the child clock estimated time (T_S_1_0) by subtracting the sum of the fixed time (ta) + transmission delay time (td),
The difference (T_S_1_0 - T_S_
2) as time correction data to the slave station, and upon receiving this, the slave station adjusts the time of the slave clock to the difference (T_S
_1_0−T_S_1) to synchronize the child clock with the master clock. (2) In a time synchronization method for a data transmission system that performs bidirectional data transmission between a master station and a slave station, a slave clock installed in the slave station is time-synchronized with a master clock installed in the master station. When synchronizing, the slave station responds to a slave clock time check command from the master station and starts at a predetermined time (t) from the frame break of the code being transmitted to the master station.
a) The time of the child clock previously read and stored in the register (
T_S_1) is transmitted as data in the frame following the break, and the master station stores the time (T_R_0) of the master clock at the time of completion of reception of the frame in a register, and then transmits it as data from the slave station. A child clock that is the sum of the arrived time (T_S_1) of the child clock, transmission delay time (td) + time from time reading of the child clock to code transmission (ta) + length of one code frame (tc). The estimated time (T_R_1_0) is calculated, and the difference (T_R_0-T_R_0_1) between this and the time (T_R_0) of the master clock at the time of completion of reception of the frame is transmitted to the slave station as time correction data, and the slave station A time synchronization method for a data transmission system, characterized in that upon receiving this, the slave clock is synchronized with the master clock by correcting the time of the slave clock by adding the difference (T_R_0-T_R_0_1).