JPS63111797A - Digital demodulator - Google Patents

Abstract

PURPOSE:To realize a digital demodulator with less adverse effect of harmonics by providing a Hilbert transform circuit shifting the carrier phase of sampled data by 90 deg. and a delay circuit retarding the transform circuit by the same time. CONSTITUTION:A modulation signal Cc is inputted to an A/D converter 2, sampled/held and converted into digital data C0. The digital data C0 is fed to a Hilbert transform circuit and a delay circuit 4, and data C2 passing through the Hilbert transform circuit becomes data whose carrier phase is deviated by 90 deg. in comparison with the data C1 passing through the delay circuit 4. The data having a different carrier phase by 90 deg. is fed to an arithmetic circuit 5, where a R-Y signal and a B-Y signal are obtained. Through the constitution above, the pre-stage filter converting the signal into digital data and the filter eliminating harmonics after demodulation are simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for transmitting a modulated signal modulated at a constant carrier frequency to -
The present invention relates to a digital demodulation device that demodulates the digital signal as it is after first converting it into a digital signal.

Conventional technology Digital demodulation of amplitude modulated or balance modulated signals has been conventionally performed. For example, when digitally demodulating a pair of color difference signals from a carrier color signal in a video signal, for example, A frequency four times the color burst frequency fsc is selected as the sampling carrier frequency, and the initial phase of this sampling carrier is set on an axis that is 180° out of phase with the burst signal axis, that is, on the B-Y axis,
By sequentially sampling based on this initial phase, the target color difference signal can be demodulated.

That is, each sampling point of the 4fsc sampling carrier is A and B as shown in FIG.

These will be points C and D. Point A is on the BY axis, and point B is on the RY axis, which is 90° in phase.

Similarly, the sampling point of 0 points is -(B-Y)
Since the point D is on the -(R-Y) axis, the data has a time series as shown in Figure 7, and can be easily demodulated by means of sign inversion and separation. . (For example, JP-A-59-158188).

Problems to be solved by the invention However, for example, home video tape recorders (
When attempting to similarly demodulate a signal that has a band approximately equal to fc both above and below the low carrier frequency fc, such as a low-frequency converted color signal recorded using the color under-one method often used in VTRs (hereinafter referred to as VTR), The following problems arise. First, as shown in FIG. 8, the frequency band YFM, which is distributed in the high frequency range of the low-frequency conversion color signal shown by the band Cc, is FM.
The luminance signal is separated by a low-pass filter indicated by LPF 1 and then demodulated. The demodulated color difference signal data is demodulated signal R-YO1B-Y as shown in RY and B-Y in FIG.
Since harmonics R-Yl and B-Yl due to carrier multiplication and sampling appear very close to O1, a very steep cutoff as shown in LPF2 is required to extract the demodulated signals R-YO and B-YO. A filter with characteristics is required.

If you try to configure it with a digital filter, it will be difficult to implement because it will be a high-order one, and if a frequency multiplexed signal like the FM luminance signal YPM remains in the upper frequency band, its harmonics will become the demodulated signal. The LPF 1 also has the disadvantage of requiring an expensive low-pass filter with steep cut-off characteristics because it enters the R-YO and B-YO bands and has an adverse effect.

Means for Solving the Problems In order to solve the above problems, the digital demodulator of the present invention includes a clock generation circuit that generates a clock n times the carrier frequency, and a clock generation circuit that generates a signal modulated at the carrier frequency. a sample-and-hold circuit that performs sampling and holding operations using a clock from the sample-and-hold circuit; a Hilbert transform circuit that shifts the phase of the data carrier sampled by the sample-and-hold circuit by 90 degrees; The modulated signal is demodulated by comprising a delay circuit that delays the data so that it is on the same time axis as the data, and an arithmetic circuit that obtains demodulated data from two data of the Hilbert transform circuit.

Effect of the Invention The present invention achieves a digital demodulation device having a wide band, low carrier frequency, and being less susceptible to adverse effects from harmonics generated by sampling and carrier multiplication even when frequency multiplexed with other signals by the above-described configuration. This also simplifies the filters used before converting to digital data and the filters used to remove harmonics after demodulation.

Embodiment Hereinafter, an embodiment of the digital demodulation device of the present invention will be described with reference to the drawings. FIG. 1 is a system diagram of a digital demodulator in one embodiment of the present invention. In FIG. 1, a modulated signal Cc is input to an A/D converter (A/D) 2, sampled and held, and then converted into digital data.

The clock generation circuit 1 generates a clock CK having a sampling frequency fs=gfc that is sufficiently higher than the carrier frequency fc of the signal Cc to prevent harmonics caused by sampling of the A/D converter 2 from folding back into the band of the input signal Cc. For example, if the signal Cc is a low-frequency conversion color signal,
If the initial phase of sampling is set on the B-Y axis, which has a 180° phase difference from the burst signal axis shown in the vector diagram in Figure 3, the sampled data CO will be expressed as the vector diagram (7) H, I, J in Figure 3. , becomes L, M, N, 0 (7) repeated data, where H=B-Y, I=-1/J(R-Y)+1/
-/l'(B-Y)J=-(RY), K=-1/
J(RY)-1/J(B-Y)L=-(B-Y),
M--1/J(RY)-1/J(B-Y)N=
RY, O= 1/J(RY) +1/J(B
-Y)...(1). The data CO is passed through a Hilbert transform circuit 3 and a delay circuit 4 having the same delay time as the Hilbert transform circuit 3, where the angular frequency of the low-frequency transform carrier is ωC, and the data C1 after passing through the delay circuit 4 is
CI = (RY)sinωc t-(B-Y)C
oS(J)Ct... (2) Then, the data C2 after passing through the Hilbert transform circuit 3 is C2=(R-Y)cosωc t-(B-Y)sinω
c t ...The data has a carrier phase shifted by 90° as shown in (3).

The arithmetic circuit 5 includes a carrier generation circuit 10. Multiplier circuit 1)~1
4. Composed of an addition circuit 15 and a subtraction circuit 16, the carrier generation circuit 10 generates sinωct and c from the clock CK.
Create carrier data of osωct, and multiply by multiplication circuit 1) ~
14, R-Y= by addition circuit 15 and subtraction circuit 16
C15inωc t + C2cosωc t...
(4) B−Y −−C1cosωc t + C2si
RY and B-Y are determined by nωc t =·(5).

To explain the above process on the frequency axis, in the data C1 that has passed through the A/D converter 2, in addition to the input data Cc, harmonics Cc' due to sampling are generated above and below the sampling frequency fs. The Hilbert transform circuit 3 is symmetrical with respect to fc, and simultaneously shifts the carrier of data Cc by 90 degrees, and at the same time has a frequency characteristic as shown by the broken line HO in FIG. 2 CI. Since R-Y and B-Y can be explained in the same way, we will only explain the demodulation process of R-Y.For example, the frequency distribution in Figure 1a is simply the modulated wave multiplied by the carrier of frequency fc. As shown in Figure 2a, the frequency 2fc generated by multiplying the demodulated wave component a0 by the carrier
The harmonic component a0'' centered on is distributed, al+al'
is the harmonic of all+a6′ caused by sampling. As for the frequency distribution shown in FIG. 1, the carrier is shifted by 90° in the Hilbert transform circuit 3, and then multiplied by the carrier shifted by 90°, so that demodulation b0. b,
On the other hand, the polarity of the harmonic ')6Z bl'' due to carrier multiplication is inverted with respect to a. Therefore, the adder 1 in Fig. 1
The result of adding a and b in step 5 is R-Y, B-Y in Figure 2.
As shown in FIG. 2, demodulated data DO is extracted from which harmonics caused by carrier multiplication have been removed. Dl is a harmonic due to sampling of DO. However, the frequency characteristics of the Hilbert transform circuit 3 are not actually all-pass type, and as shown by HO in Fig. 2, the gain becomes O at frequencies that are integral multiples of 2fC, so R-Y, B-Y There remain some harmonic waves DO' and D1° due to carrier multiplication. By using a Hilbert transformer in this way, modulated waves with carrier phases different by 90 degrees are created, and harmonics due to carrier multiplication are removed by demodulating and adding two modulated waves with carrier phases different by 90 degrees. can do. Note that if the signal is not a quadrature two-phase balanced modulation wave but a simple balanced modulation wave or an amplitude modulation wave like a low frequency conversion color signal, only one adder/subtractor is required, and the carrier generation circuit 10 repeatedly generates a single code. Multiplier 1
) to 14 are not particularly necessary if a digital circuit that repeatedly performs several code conversions is used.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a system diagram of a digital demodulator in a second embodiment of the present invention. In the following description, parts that perform the same operations as those in other drawings will be designated by the same numbers and symbols, and redundant description will be omitted. In FIG. 4, the Hilbert transform circuit 3 is comprised of delay elements 21-32, amplifier circuits 40-43, and an adder circuit 81. Each of the delay elements 21 to 32 delays the clock CK generated by the clock generation circuit 1 by one clock. The arithmetic circuit 5 includes an amplifier circuit 44.45, a switching circuit 50.51,
It is composed of a timing circuit 60, sign inversion circuits 70 to 73, and addition circuits 82 and 83. The portion corresponding to the delay circuit 4 of the embodiment of FIG. 1 is the Hilbert transform circuit 3 of FIG.
delay elements are shared and delay data C1 is obtained from the intermediate tap. FIG. 5 shows the timing of each part in FIG. 4. Similar to the embodiment shown in FIG.
) H, I shown by the formula.

When L, M, N, O are repeatedly output to J, in the order of L, M, N, output C2 of the Hilbert transform circuit 3 is obtained by phase shifting the carrier of C1 by 90 degrees to J, L, M, N.

It is output in the order of 0, H, and I. The calculation circuit 5 calculates and outputs color difference signal data RY and BY from the data C1 and C2. The sign inversion circuits 70 to 73 perform sign inversion processing using the pulses P1 to P4 from the timing circuit 60, and when the input pulse is at the digital level "1", the input data is output as is, and when the input pulse is at the digital level "0". Sometimes the sign of data is inverted and output. Switching circuit 50.
Reference numeral 51 selects the outputs of the sign inverting circuit and the amplifying circuit 44 and 45, which are connected to their inputs, using the control data CNT from the timing circuit 60, and outputs the demodulated color difference signal data R-.
I have obtained Y and B-Y. Pulses P, -P4 and control data CNT are all generated by the timing circuit 60 using the clock CK from the clock generation circuit 1. As described above, the arithmetic circuit 5 in the second embodiment of the present invention is replaced by the amplifier circuit 4.
4. By configuring the sign inverting circuits 70 to 73, addition circuits 82 and 83, switching circuits 50 and 51, and timing circuit 60, it is realized by a simple digital circuit without using a multiplication circuit.

Effects of the Invention As described above, the digital demodulation device of the present invention includes a clock generation circuit that generates a clock n times the carrier frequency, and a sampling and holding operation of a signal modulated at the carrier frequency using the clock from the clock generation circuit. a Hilbert transform circuit that shifts the phase of the data carrier sampled by the sample hold circuit by 90 degrees, and a Hilbert transform circuit that shifts the phase of the carrier of the data sampled by the sample hold circuit, and a Hilbert transform circuit that shifts the phase of the carrier of the data sampled by the sample hold circuit so that the sampled modulation data is on the same time axis as the output data of the Hilbert transform circuit. Since it is composed of an arithmetic circuit that obtains demodulated data from two data: a delay circuit that delays and the Hilbert transform circuit, it prevents harmonics caused by carrier multiplication and harmonics caused by sampling from folding back into the band of demodulated data, and modulates the data. It is possible to reduce the specs of the filter in the previous stage that converts the signal into digital data, and it can be realized at a low cost.It is also possible to simplify or remove the filter for removing harmonics by carrier multiplication for the data after demodulation. It has the effect of making it possible. moreover,
A carrier generating circuit generates two carriers: a carrier of the output data of the delay circuit and a carrier having a phase difference of 90' with respect to the carrier, and the output data of the delay circuit and the Hilbert transform circuit respectively. By having a multiplier circuit that multiplies with , and one or more adder/subtracter circuits that add or subtract the multiplication results of the multiplier circuits, the arithmetic circuit can be configured as a digital circuit with stable characteristics, and the characteristics of the demodulator can be stabilized. effective. Furthermore, the delay circuit shares the delay element built into the Hilbert transform circuit, and by providing a tap in the middle of the total number of delay stages of the delay element to take out data, the delay circuit is omitted and the circuit configuration of the device is simplified. It has the effect of Further, the arithmetic circuit includes a sign inverting circuit capable of changing the sign of the output data of the Hilbert transform circuit and the output data of the delay circuit, an adding circuit that adds data, and an amplifier circuit that amplifies data with a constant gain; A multiplication circuit is used by comprising a switching circuit that switches and outputs the data processed by the sign inversion circuit, addition circuit, and amplifier circuit, and a timing circuit that generates a control pulse to control the sign inversion circuit and the switching circuit. This has the effect of configuring an arithmetic circuit without any unnecessary processing, and it is also possible to configure a digital demodulation device with a simpler digital circuit.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of a digital demodulator in an embodiment of the present invention, Fig. 2 is a frequency distribution diagram of each part of data in Fig. 1, and Fig. 3 is a diagram of the A/D converter of Fig. 1. A vector diagram showing the sampling timing, FIG. 4 is a system diagram of the digital demodulator in the second embodiment of the present invention, FIG. 5 is a timing diagram showing the data timing of each part of FIG. 4, and FIG. is a vector diagram showing the sampling timing of a conventional digital demodulator, FIG. 7 is a timing diagram of data obtained by the sampling timing of a conventional digital demodulator, and FIG. 8 is a vector diagram showing the frequency of demodulated data in a conventional digital demodulator. It is a frequency distribution diagram for explaining distribution. 1... Clock generation circuit, 2... A/
D converter, 3... Hilbert conversion circuit, 4
... Delay circuit, 5 ... Arithmetic circuit, 10
...Carrier generation circuit, 1) to 14...
・Multiplication circuit, 15... Addition circuit, 16...
...Subtraction circuit, 21-32...Delay element, 40
~45...Amplification circuit, 50~51...
Switching circuit, 60... Timing circuit, 70-7
3...Sign inversion circuit, 81-83...
addition circuit. Name of agent Patent attorney Toshio Nakao 1 person Figure 1 Figure 2 0 2fc 6fc l/f
c Fig. 3 R-Y - (R-y) Fig. 6 - (ρ-Y) Fig. 7 ABCDABCD Fig. 8 2fc dfCMR bed

Claims (4)

[Claims] (1) A clock generation circuit that generates a clock n times the carrier frequency, a sample hold circuit that samples and holds a signal modulated at the carrier frequency using the clock from the clock generation circuit, and the sample hold circuit. a Hilbert transform circuit that shifts the phase of the data carrier sampled by 90°;
Digital demodulation comprising a delay circuit that delays the sampled modulated data so that it is on the same time axis as the output data of the Hilbert transform circuit, and an arithmetic circuit that obtains demodulated data from two data of the Hilbert transform circuit and the delay circuit. Device. (2) The arithmetic circuit includes a carrier generation circuit that generates two carriers: the carrier of the output data of the delay circuit and a carrier having a phase difference of 90° with respect to the carrier, and a delay circuit and a Hilbert transform circuit that respectively generate the two carriers. The digital demodulation device according to claim 1, further comprising a multiplication circuit that multiplies the output data of the multiplication circuit, and one or more addition/subtraction circuits that add or subtract the multiplication results of the multiplication circuits. . (3) Claim (1) characterized in that the delay circuit shares a delay element built in the Hilbert transform circuit, and has a configuration in which a tap is provided in the middle of the total number of delay stages of the delay element to extract data. Digital demodulator as described. (4) The arithmetic circuit includes a sign inversion circuit that can switch the sign of the output data of the Hilbert transform circuit and the output data of the delay circuit, an addition circuit that adds data, and an amplifier circuit that amplifies data with a constant gain; A patent claim comprising: a switching circuit that switches and outputs the data processed by the sign inversion circuit, the addition circuit, and the amplification circuit; and a timing circuit that generates a control pulse to control the sign inversion circuit and the switching circuit. The digital demodulator according to the range (1).