JPS6310889B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a pattern having a line width in the submicron range.

In recent years, in order to improve the degree of integration and high speed of semiconductor devices, pattern forming technology with line widths in the submicron region has been required.

However, when it comes to forming patterns with line widths in the submicron region, the optimal exposure dose varies for each line width and even for patterns with different density levels. Therefore, it is usually impossible to form a pattern over the entire surface with high dimensional accuracy.

Now, let us consider the case where a pattern as shown in FIG. 1 is desired.

1 is a sample and 2 is a pattern groove. Since patterns 2 of the same width are formed in portions with different densities, the optimum exposure doses differ from each other in the conventional method, making it difficult to form these patterns as designed.

Therefore, the present inventors separately proposed a pattern forming method as shown in FIG. 2 to solve such pattern forming problems.

The method will be explained with reference to the process illustrative sectional view of FIG.

(1) A resist 3 is applied to the sample 1, and a first pattern of simply repeated lines and spaces is exposed 4.

(2) Develop the resist 3 to form the spaces 10 of the first pattern.

(3) A resist 11 is applied thereon, and a second pattern is exposed 12 in which the minimum space width is larger than the space width of the first pattern.

(4) Develop the resist 11 to form the spaces 13 of the second pattern.

(5) By etching sample 1 using resist 3 and resist 11 as masks, recesses 14 and 1 are etched.
After forming the resists 3 and 11, the resists 3 and 11 are peeled off.

The pattern obtained in this way is resist 3
The region is formed by the logical product of the spaces of the first pattern of the resist 11 and the spaces of the second pattern of the resist 11, and the same groove width is obtained for the grooves 14 in the dense portions and the grooves 15 in the ridged portions.

The problem here is the alignment accuracy between the first pattern and the second pattern.

Regarding the rotational misalignment between the first pattern and the second pattern, the inventors used a simple repeating line-and-space pattern for the alignment mark of the second pattern, and We have separately proposed a method for removing rotational deviation using a moiré pattern with the first pattern.

Incidentally, in semiconductor devices and the like, it is common to form a large number of chips on one wafer. Therefore, the second pattern forming mask has the same pattern repeated as shown in FIG. In the same figure, 31 is a glass substrate formed of transparent glass or the like, and this glass substrate 3
1, a plurality of pellets 32 having a second pattern F of the same shape formed of chromium metal or the like are arranged in the X and Y directions to form a photomask 33.
is configured. Normally, chip fabrication using the photomask 33 configured as described above is performed at the fourth stage.
As shown in Figure a, a plurality of chips 35 are simultaneously formed by applying a resist to the surface of a wafer 34 and exposing the resist to light through a photomask 33 . The plurality of chips 35 thus formed on the wafer 34 are cut into chips 35 by a wafer scriber, as shown in FIG. 4b, to produce several hundred chips at a time. become.

To manufacture this photomask 33 , first, a pattern F' having a size n times (usually 10 times) the actual size of the pattern F is formed on a reticle using a pattern generator. Next, this reticle pattern F' is reduced to 1/n using a photorepeater, and
As shown in FIG. 3, the same pattern F is formed on each pellet 32 repeatedly in the X direction and the Y direction, thereby forming a photomask 33 .

As mentioned earlier, if you remove the rotational deviation between the first and second patterns of a simple line and space, you can obtain a good product with a 50% probability without any other alignment. . However, this is only when a large number of wafers are processed;
If we look at the wafers being released, either all the chips are good or all the chips are defective.
This becomes a problem when the number of wafers to be processed is small.

An object of the present invention is to provide a pattern forming method with good line width accuracy, which ensures that half of the chips on a wafer are good products by only simple alignment. That is, according to the present invention, there is provided a step of forming a first pattern of simply repeated lines and spaces, and a minimum space width on the first pattern is smaller than the space width of the first pattern. and changing the first pattern by forming a second pattern that is larger than the second pattern, the second pattern forming mask is such that the pellets in the second pattern are larger than the first pattern. A pattern forming method can be obtained that uses repeat pitches arranged at an odd number multiple of half the repeat period.

The pattern forming method according to the present invention will be explained in detail below with reference to the drawings. 5 and 6 are diagrams for explaining the present invention. FIG. 5 is a plan view of a desired chip pattern, and FIG. 6 is a sectional view for explaining the process.

(1) A first pattern of simple repeating lines and spaces is formed on the resist 3 coated on the sample 1, and the other resist 11 is formed on top of it.
is applied and covered with an exposure mask 61. This exposure mask 61 has a large number of pellets 62 and 63, and patterns 64 and 65 of the same shape are formed on these pellets, and these patterns are similar to the line and space pattern of the first pattern. It is repeated at a pitch of (2n-1)l, which is an odd multiple of half l of the pattern repetition period (where n is an arbitrary integer). Next, the rotational deviation between the pattern of the exposure mask 61 and the line and space pattern of the first pattern is removed, and exposure is performed.

(2) Develop the resist 11.

At this time, the half chips are in the desired positional relationship as shown in 66.

(3) If sample 1 is etched using resists 3 and 11 as masks, and resists 3 and 11 are peeled off,
Good chips such as 66 and defective chips such as 67 are obtained equally.

As described above, according to the present invention, the line
A simple alignment that eliminates the rotational deviation between the first pattern and the second pattern of AND SPACE makes it possible to form a pattern with high line width accuracy, ensuring that half of the chips on the wafer are good.

In the description, an exposure mask is used for producing the second pattern, but it goes without saying that the present invention is also applicable to exposure without using a mask, such as electron beam exposure.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing the desired pattern, and Fig. 2 is a cross-sectional view explaining the process of forming the pattern shown in Fig. 1 with high line width accuracy. Figure 2 shows the state in which line and space is repeatedly exposed, Figure 2 shows the developed state, Figure 3 shows the state in which another resist is applied,
Diagram 4 showing a state in which a complex pattern is exposed.
5 is a diagram showing a developed state, and 5 is a diagram showing a state after etching and peeling off the resist. FIG. 3 is a plan view showing a general photomask for pattern production, and FIGS. 4a and 4b are plan views showing wafers and chips manufactured using the photomask shown in FIG. 3. FIG. 5 is a plan view showing the desired chip pattern;
FIG. 6 is a process explanatory sectional view for explaining the present invention, 1 is a diagram showing a state in which the exposure mask of the present invention is covered over the first pattern of line and space, and 2 is a diagram showing the developed state. Figure 3 shows the state after etching and the resist has been peeled off. In the figure, 1 is a sample, 2 is a groove of a desired pattern, 3 and 11 are resists, 4 and 12 are exposed, 1
0 and 13 are resist spaces, 14 and 15 are grooves obtained, 31 is a glass substrate, 32 is a pellet,
33 is a photomask, 34 is a wafer, 35 is a chip, 61 is an exposure mask, 62 and 63 are pellets, 64 and 65 are second patterns, and 66 and 67 are chips.

Claims (1)

[Claims] 1. Forming a first pattern of simply repeated lines and spaces, and forming a second pattern on the first pattern, the minimum space width of which is larger than the space width of the first pattern. A pattern forming method comprising at least the step of forming and changing the first pattern,
A pattern forming method characterized in that the second pattern forming mask uses a mask in which pellets are arranged at a repeat pitch that is an odd number multiple of half the repeat period of the first pattern.