JPS63107148A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63107148A JPS63107148A JP61252976A JP25297686A JPS63107148A JP S63107148 A JPS63107148 A JP S63107148A JP 61252976 A JP61252976 A JP 61252976A JP 25297686 A JP25297686 A JP 25297686A JP S63107148 A JPS63107148 A JP S63107148A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- layer
- sealing member
- synthetic resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000007789 sealing Methods 0.000 claims abstract description 39
- 229920003002 synthetic resin Polymers 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000000057 synthetic resin Substances 0.000 claims abstract description 12
- 239000003822 epoxy resin Substances 0.000 abstract description 10
- 239000010931 gold Substances 0.000 abstract description 10
- 229920000647 polyepoxide Polymers 0.000 abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000006835 compression Effects 0.000 abstract description 3
- 238000007906 compression Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229920005992 thermoplastic resin Polymers 0.000 abstract description 3
- 239000006023 eutectic alloy Substances 0.000 abstract description 2
- 230000006698 induction Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000007767 bonding agent Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 19
- 239000012790 adhesive layer Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、印刷配線板上に半導体素子を搭載しその半導
体素子を封止した半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which a semiconductor element is mounted on a printed wiring board and the semiconductor element is sealed.
（従来の技術）
従来、このような分野の技術としては、実公昭５５−４
７０６５号公報に記載されるものがあった。以下、その
構成を図を用いて説明する。(Prior art) Conventionally, as a technology in this field,
There was one described in Publication No. 7065. The configuration will be explained below using figures.
第２図は従来の半導体装置の一構成例を示す平面図、お
よび第３図はその縦断面図である。FIG. 2 is a plan view showing an example of the configuration of a conventional semiconductor device, and FIG. 3 is a longitudinal sectional view thereof.
この半導体装置は印刷配線板（以下、プリント基板とい
う）を有し、そのプリント基板１の表面には導電性の回
路パターン２と台パターン３とが形成されている。プリ
ント基板１上には半導体素子４が搭載され、それがエポ
キシ樹脂等の接着剤５で固着されている。半導体素子４
の電極部はワイヤ６によって回路パターン２と接続され
ている。This semiconductor device has a printed wiring board (hereinafter referred to as a printed circuit board), and a conductive circuit pattern 2 and a base pattern 3 are formed on the surface of the printed circuit board 1. A semiconductor element 4 is mounted on a printed circuit board 1, and is fixed with an adhesive 5 such as epoxy resin. Semiconductor element 4
The electrode portion is connected to the circuit pattern 2 by a wire 6.
半導体素子４の周囲の回路パターン２及び台パターン３
上には、封止枠７が載置され、それが接着剤８によりプ
リント基板１上に接着されている。Circuit pattern 2 and base pattern 3 around the semiconductor element 4
A sealing frame 7 is placed on top and is adhered onto the printed circuit board 1 with an adhesive 8.
封止枠７内にはエポキシ樹脂等からなる樹脂部材９が充
填され、その樹脂部材９によって半導体素子４とその半
導体素子４および回路パターン２の接続箇所とが樹脂封
止されている。なお、プリント基板１上に形成された台
パターン３は、プリン上基板１上の表面とそこに形成さ
れた回路パターン２との高さの差によって生じる封止枠
７下面の間隙を極力少なくし、樹脂部材９の封止枠７下
面からの流出を防止するためのものでおる。The sealing frame 7 is filled with a resin member 9 made of epoxy resin or the like, and the semiconductor element 4 and the connection portion between the semiconductor element 4 and the circuit pattern 2 are sealed with the resin member 9. Note that the base pattern 3 formed on the printed circuit board 1 minimizes the gap between the lower surface of the sealing frame 7 caused by the difference in height between the surface of the printed circuit board 1 and the circuit pattern 2 formed thereon. This is to prevent the resin member 9 from flowing out from the bottom surface of the sealing frame 7.
以上のような半導体装置の製造方法を説明する。A method of manufacturing the semiconductor device as described above will be explained.
先ず、プリント基板１上に半導体素子４を固着すると共
に、その半導体素子４と回路パターン２とをワイヤ６で
接続する。さらに、半導体素子４の周囲に封止枠７を固
定する。First, the semiconductor element 4 is fixed onto the printed circuit board 1, and the semiconductor element 4 and the circuit pattern 2 are connected with the wires 6. Furthermore, a sealing frame 7 is fixed around the semiconductor element 4.
次に、プリント基板１及び半導体素子４を１５０’Ｃ程
度に加熱し、第４図に示すようなエポキシ樹脂を冷間成
型（加圧成型）してなるペレット１０を、封止枠７内に
載せる。すると、ペレット１０は熱により液状化し、封
止枠７内に充填され、その後硬化して封止部材９となり
、半導体素子４及びワイヤ６を樹脂封止する。Next, the printed circuit board 1 and the semiconductor element 4 are heated to about 150'C, and a pellet 10 made of cold molded (pressure molded) epoxy resin as shown in FIG. 4 is placed inside the sealing frame 7. I'll put it on. Then, the pellet 10 is liquefied by heat, filled into the sealing frame 7, and then hardened to become the sealing member 9, which seals the semiconductor element 4 and the wire 6 with the resin.
このような製造方法によれば、プリント基板１上に直接
半導体素子４を固定し、それを樹脂封止するため、小型
化に適する半導体装置を得ることができる。According to such a manufacturing method, since the semiconductor element 4 is directly fixed onto the printed circuit board 1 and sealed with resin, a semiconductor device suitable for miniaturization can be obtained.
（発明が解決しようとする問題点）
しかしながら、上記構成の半導体装置では、半導体素子
４等を樹脂部材９で封止しているので、樹脂部材９の高
さ方向の厚みをおる程度大きくしなければ、水分、アル
ミ配線腐食性イオン等の浸入により、半導体素子４の配
線に用いられているアルミ配線の腐食や、リーク等が発
生するおそれがあざ。さらに、封止状態のばらつきが生
じることからも、樹脂部材９の厚みをおる程度大きくし
ておく必要がある。そのため、この種の半導体装置を薄
板状のＩＣカード等に搭載する場合、薄形化の点につい
て充分満足のゆくものが得られなかった。(Problems to be Solved by the Invention) However, in the semiconductor device having the above configuration, since the semiconductor element 4 etc. are sealed with the resin member 9, the thickness of the resin member 9 must be made large enough to pass through the thickness in the height direction. For example, the aluminum wiring used for the wiring of the semiconductor element 4 may be corroded or leakage may occur due to the infiltration of moisture, aluminum wiring corrosive ions, etc. Furthermore, since variations in the sealing state occur, it is necessary to increase the thickness of the resin member 9 to some extent. Therefore, when this type of semiconductor device is mounted on a thin IC card or the like, it has not been possible to achieve a sufficiently satisfactory thickness.
本発明は、前記従来技術が持っていた問題点として、薄
形化の点について解決した半導体装置を提供するもので
ある。The present invention provides a semiconductor device that solves the problem of thinning, which is a problem that the prior art had.
（発明が解決しようとする手段〉
本発明は、前記問題点を解決するために、導電性の回路
パターンが形成されたプリント基板と、前記プリント基
板上に固着され前記回路パターンに接続された半導体素
子とを備え、前記半導体素子とその半導体素子および前
記回路パターンの接続箇所とが封止された半導体装置に
おいて、金属層及び合成樹脂層を有するフィルム状の封
止部材で、前記半導体素子および接続箇所を気密封止し
たものである。(Means to be Solved by the Invention) In order to solve the above problems, the present invention provides a printed circuit board on which a conductive circuit pattern is formed, and a semiconductor fixed on the printed circuit board and connected to the circuit pattern. In a semiconductor device comprising a semiconductor element and a connection point between the semiconductor element and the circuit pattern, the semiconductor element is sealed with a film-like sealing member having a metal layer and a synthetic resin layer. The area is hermetically sealed.
（作 用）
本発明によれば、以上のように半導体装置を構成したの
で、封止部材はその厚みが薄く、しかも水分等の浸入阻
止力が大きいため、高さ方向の厚みの縮小化を可能にさ
せる。従って前記問題点を除去できるのである。(Function) According to the present invention, since the semiconductor device is configured as described above, the sealing member is thin and has a large ability to prevent water from entering, so that the thickness in the height direction can be reduced. make it possible. Therefore, the above-mentioned problem can be eliminated.
（実施例）
第１図は本発明の第１の実施例を示す半導体装置の縦断
面図である。(Embodiment) FIG. 1 is a longitudinal sectional view of a semiconductor device showing a first embodiment of the present invention.
この半導体装置は絶縁性のプリント基板２０を有し、そ
のプリント基板２０はガラスエポキシ樹脂板、セラミッ
ク板、絶縁処理された金属板、ガラス板、石英板、熱可
塑性樹脂板、フェノール樹脂を紙に含浸ざじた紙フエノ
ール板、エポキシ樹脂を紙に含浸させた紙エポキシ板等
で形成されている。プリント基板２０の表面には銅箔等
からなる導電性の回路パターン２１と素子搭載部２２と
が形成されている。This semiconductor device has an insulating printed circuit board 20, and the printed circuit board 20 is made of a glass epoxy resin board, a ceramic board, an insulated metal board, a glass board, a quartz board, a thermoplastic resin board, or a phenol resin on paper. It is made of impregnated paper phenol board, paper epoxy board impregnated with epoxy resin, etc. A conductive circuit pattern 21 made of copper foil or the like and an element mounting section 22 are formed on the surface of the printed circuit board 20.
回路パターン２１はその内方の接続部２１ａが金Ａｕや
銀へ（１等でメッキ処理され、さらにその接続部２１ａ
を除く他の部分がエポキシ樹脂等からなるソルダーレジ
ストの保護膜２３で被覆されている。この保護膜２３は
回路パターン２１を機械的な不都合、例えば傷等による
断線、水分等による腐食やショート等を防止して信頼性
を向上させる等の目的で、シルク印刷法等によってプリ
ント基板２０上に形成されるものであるが、形成しなく
てもよい。The inner connection portion 21a of the circuit pattern 21 is plated with gold (Au or silver), and the connection portion 21a is plated with gold (Au) or silver (first grade).
The other portions except for the portions are covered with a protective film 23 of solder resist made of epoxy resin or the like. This protective film 23 is applied to the printed circuit board 20 by silk printing or the like in order to improve reliability by preventing mechanical problems such as disconnection due to scratches, corrosion due to moisture, short circuits, etc., of the circuit pattern 21. However, it does not have to be formed.
さらに保護膜２３上、おるいはその保護膜２３か形成さ
れていないときには回路パターン２１上の封止部材固着
予定箇所には、単層あるいは複数層の熱可塑１生樹脂か
らなる接着層２４が形成されている。Further, on the protective film 23, or when the protective film 23 is not formed, on the circuit pattern 21, an adhesive layer 24 made of a single layer or multiple layers of thermoplastic raw resin is placed on the circuit pattern 21 where the sealing member is to be fixed. It is formed.
この接着剤２４は、プリント基板２０における端子部等
の接続導電部を除いて全面に形成してもよい。This adhesive 24 may be formed on the entire surface of the printed circuit board 20 except for connection conductive parts such as terminal parts.
素子搭載部２２上には半導体素子２５が搭載され、それ
が導電性エポキシ樹脂等の接着剤や、金Ａｕ −シリコ
ンＳｉ共晶合金法等によって固着されている。A semiconductor element 25 is mounted on the element mounting portion 22, and is fixed using an adhesive such as a conductive epoxy resin, a gold-Au-silicon-Si eutectic alloy method, or the like.
半導体素子２５の電極部はアルミニウム八β、金Ａｕ等
のワイヤ２６によって回路パターン２１の接続部２１ａ
と接続されている。The electrode portion of the semiconductor element 25 is connected to the connection portion 21a of the circuit pattern 21 by a wire 26 made of aluminum 8β, gold Au, etc.
is connected to.
接着層２４上には、予めプレス等によって凹部が形成さ
れたフィルム状の封止部材２７が溶着されている。この
封止部材２７は、その断面図である第５図に示すように
、薄板状あるいはメツシュ状の金属層２７−１と、その
下面に形成された熱可塑性樹脂等の合成樹脂層２７−２
からなる２層構造をなし、それに形成された凹部が半導
体素子２５及びワイヤ２６をおおうような形で、該合成
樹脂層２７−２が加熱圧着、高周波誘導体加熱、あるい
は超音波１辰動等により接着層２４を介してプリント基
板２０上に溶着されている。On the adhesive layer 24, a film-like sealing member 27 in which a recess is formed in advance by pressing or the like is welded. As shown in FIG. 5, which is a cross-sectional view of the sealing member 27, the sealing member 27 includes a thin plate-like or mesh-like metal layer 27-1, and a synthetic resin layer 27-2 such as a thermoplastic resin formed on the lower surface of the metal layer 27-1.
The synthetic resin layer 27-2 has a two-layer structure, and the recess formed therein covers the semiconductor element 25 and the wire 26, and the synthetic resin layer 27-2 is heated by heat compression bonding, high-frequency induction heating, or ultrasonic one-stroke, etc. It is welded onto the printed circuit board 20 via an adhesive layer 24.
以上のように構成される半導体装置の製造方法について
説明する。A method of manufacturing a semiconductor device configured as described above will be described.
先ず、プリント基板２０の素子搭載部２２上に半導体素
子２５を接着剤等で固着する。ざらに、半導体素子２５
の電極部と回路パターン２１の接続部２１ａとをワイヤ
２６で接続する。First, the semiconductor element 25 is fixed onto the element mounting portion 22 of the printed circuit board 20 using an adhesive or the like. Roughly, semiconductor element 25
The electrode portion and the connecting portion 21a of the circuit pattern 21 are connected with a wire 26.
次に、例えば不活性ガスＮ２等の雰囲気下において、予
めプレス等で凹部を形成しておいた封止部材２７をその
凹部が半導体素子２５上にくるように位置決めしてプリ
ント基板２０の接着層２４上に載置する。この際、位置
決め用のマーク等を施しておけば、封止部材２７の位置
決めが簡易的確に行える。Next, under an atmosphere of inert gas N2 or the like, the sealing member 27 in which a recess has been formed in advance by pressing or the like is positioned so that the recess is above the semiconductor element 25, and the adhesive layer of the printed circuit board 20 is 24. At this time, if a positioning mark or the like is provided, positioning of the sealing member 27 can be easily and accurately performed.
その後、加熱圧着等によって封止部材２７底部の合成樹
脂層２７−２と接着層２４とを溶着する。これにより、
半導体素子２５、ワイヤ２６、および回路パターン２１
の接続部２１ａは封止部材２７により気密封止され、第
１図のような半導体装置が得られる。Thereafter, the synthetic resin layer 27-2 at the bottom of the sealing member 27 and the adhesive layer 24 are welded together by heat compression bonding or the like. This results in
Semiconductor element 25, wire 26, and circuit pattern 21
The connecting portion 21a is hermetically sealed by a sealing member 27, and a semiconductor device as shown in FIG. 1 is obtained.
本実施例では、フィルム状の封止部材２７を用いて半導
体素子２５等を封止するようにしたので、高さ方向の厚
さを従来のものよりも薄くできる。しかも封止部材２７
中に金属層２７−１が設けられているので、外部に対す
る機械的強度も大きく、へこみ等を最小限度に防止でき
るばかりか、その金属層２７−１を薄板状で形成した場
合には水分等の侵入をほぼ完全に防止できる。また、封
止部材２７の固着に際して部分的に加熱等を施して合成
樹脂層２７を接着層２４に溶着させることができるので
、半導体素子２５に対する熱的悪影響を与えることもな
い。In this embodiment, since the semiconductor element 25 and the like are sealed using the film-like sealing member 27, the thickness in the height direction can be made thinner than the conventional one. Moreover, the sealing member 27
Since the metal layer 27-1 is provided inside, it has high mechanical strength against the outside and can not only prevent dents etc. to a minimum, but also prevent moisture etc. when the metal layer 27-1 is formed in a thin plate shape. Intrusion can be almost completely prevented. Moreover, since the synthetic resin layer 27 can be welded to the adhesive layer 24 by partially applying heat or the like when fixing the sealing member 27, there is no adverse thermal effect on the semiconductor element 25.
第６図は本発明の第２の実施例を示す半導体装置の縦断
面図でおる。FIG. 6 is a longitudinal sectional view of a semiconductor device showing a second embodiment of the present invention.
この半導体装置が第１図のものと異なる点は、保護膜２
３上の、あるいはそれが形成されていない場合にはプリ
ント基板２０上の、接続部２１ａ外周に円形、四角形等
の保護枠３０をエポキシ樹脂等の接着剤３１で接着した
ことで市る。このような保護枠３０を設ければ、機械的
外力による封止部材２７のへこみ等から、内部のワイヤ
２６等を保護できる。The difference between this semiconductor device and the one in FIG. 1 is that the protective film 2
3 or, if not formed, on the printed circuit board 20, a protective frame 30 of a circular or square shape is adhered to the outer periphery of the connecting portion 21a using an adhesive 31 such as epoxy resin. By providing such a protection frame 30, it is possible to protect the internal wire 26 and the like from denting of the sealing member 27 due to external mechanical force.
第７図は本発明の第３の実施例を示す半導体装置の縦断
面図である。FIG. 7 is a longitudinal sectional view of a semiconductor device showing a third embodiment of the present invention.
この半導体装置では、積層構造のプリント基板２０の層
間に回路パターン２１が形成されており、しかもそのプ
リント基板２０においてざくり加工等によって凹状の収
納部３２が形成され、その収納部３２底面に素子搭載部
２２が形成されている。そして素子搭載部２２上に固着
された半導体素子２５が収納部３２内に収容され、ワイ
ヤ２６によって回路パターン２１の接続部２１ａと接続
されている。ざらに、フィルム状の封止部材２７は平板
状をなし、接着層２４によって収納部３２上端の開口部
に溶着されている。In this semiconductor device, a circuit pattern 21 is formed between the layers of a printed circuit board 20 having a laminated structure, and a recessed housing portion 32 is formed in the printed circuit board 20 by a hollowing process or the like, and an element is mounted on the bottom surface of the housing portion 32. A portion 22 is formed. The semiconductor element 25 fixed on the element mounting part 22 is housed in the housing part 32 and connected to the connecting part 21a of the circuit pattern 21 by a wire 26. Roughly speaking, the film-like sealing member 27 has a flat plate shape, and is welded to the opening at the upper end of the storage portion 32 with the adhesive layer 24 .
このような半導体装置では、半導体素子２５がプリント
基板２０に埋設される形で搭載されているため、さらに
薄形化できる。In such a semiconductor device, since the semiconductor element 25 is embedded in the printed circuit board 20, it can be made even thinner.
本発明は図示の実施例に限定されず、種々の変形が可能
である。その変形例としては、例えば次のようなものが
おる。The present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.
■ 封止部材２７は種々の形状に変形可能であり、また
その断面構造は例えば第８図に示すように、金属層２７
−１上にさらに合成樹脂＠２７−３を積層した３層構造
にしたり、あるいは４層以上の構造にしてもよい。(2) The sealing member 27 can be deformed into various shapes, and its cross-sectional structure can be changed, for example, as shown in FIG.
A three-layer structure in which synthetic resin @27-3 is further laminated on -1, or a four-layer structure or more may be used.
■ 封止部材２７中の金属層２７−１に透過窓を形成す
る等しておけば、ＥＰＲＯＨ等の封止にも適用できる。(2) If a transparent window is formed in the metal layer 27-1 in the sealing member 27, it can also be applied to sealing of EPROH and the like.
■ 接着層２４は封止部材２７の接着力を補強するため
のものである。そのため、封止部材２７における合成樹
脂層２７−２の接着力が大きければ、省略してもよい。(2) The adhesive layer 24 is for reinforcing the adhesive force of the sealing member 27. Therefore, if the adhesive force of the synthetic resin layer 27-2 in the sealing member 27 is strong, it may be omitted.
■ 半導体素子２５上に、シリコン樹脂、ポリイミド樹
脂等をボッティング等の方法により形成してあけば、信
頼性がより向上する。同様に、第７図の収納部３２内に
エポキシ樹脂、シリコン樹脂等を充填してから封止部材
２７で気密封止しても、信頼性がより高くなる。(2) Reliability can be further improved by forming silicone resin, polyimide resin, etc. on the semiconductor element 25 by a method such as botting. Similarly, even if the storage portion 32 shown in FIG. 7 is filled with epoxy resin, silicone resin, etc. and then hermetically sealed with the sealing member 27, the reliability will be higher.
（発明の効果）
以上詳細に説明したように、本発明の半導体装置によれ
ば、フィルム状の封止部材で半導体素子等を気密封止し
たので、薄形化を向上させることができると共に、水分
の侵入等を的確に防止して信頼性の向上が図れる。(Effects of the Invention) As described in detail above, according to the semiconductor device of the present invention, since the semiconductor element and the like are hermetically sealed with the film-like sealing member, it is possible to improve the thickness reduction, and Reliability can be improved by accurately preventing moisture from entering.
第１図は本発明の第１の実施例を示す半導体装置の縦断
面図、第２図は従来の半導体装置の平面図、第３図は第
２図の縦断面図、第４図は従来のペレットの斜視図、第
５図は第１図の封止部材の断面図、第６図及び第７図は
本発明の第２、第３の実施例を示す半導体装置の縦断面
図、第８図は第６図の変形断面図である。
２０・・・・・・プリント基板、２１・・・・・・回路
パターン、２２・・・・・・素子搭載部、２４・・・・
・・接着層、２５・・・・・・半導体素子、２６・・・
・・・ワイヤ、２７・・・・・・封止部材、２７−１・
・・・・・金属層、２７−２．２７−３・・・・・・合
成樹脂層、３０・・・・・・保衾枠、３２・・・・・・
収納部。
出願人代理人 柿 本 恭 成従来の半導体装
置の平面図
第２図
第２図の縦断面図
第３図
ペレット
第４図
第１図Ｏ封上部材断面図
第５図FIG. 1 is a vertical cross-sectional view of a semiconductor device showing a first embodiment of the present invention, FIG. 2 is a plan view of a conventional semiconductor device, FIG. 3 is a vertical cross-sectional view of FIG. 2, and FIG. 4 is a conventional semiconductor device. 5 is a sectional view of the sealing member of FIG. 1, and FIGS. 6 and 7 are longitudinal sectional views of semiconductor devices showing second and third embodiments of the present invention. FIG. 8 is a modified sectional view of FIG. 6. 20... Printed circuit board, 21... Circuit pattern, 22... Element mounting section, 24...
...Adhesive layer, 25...Semiconductor element, 26...
... Wire, 27 ... Sealing member, 27-1.
...Metal layer, 27-2.27-3...Synthetic resin layer, 30...School frame, 32...
Storage department. Applicant's agent Yasushi Kakimoto Plan view of conventional semiconductor device Fig. 2 Vertical sectional view of Fig. 2 Fig. 3 Pellet Fig. 4 Fig. 1 Cross-sectional view of O-sealing member Fig. 5
Claims (1)
印刷配線板上に固着され前記回路パターンに接続された
半導体素子とを備え、前記半導体素子とその半導体素子
および前記回路パターンの接続箇所とが封止された半導
体装置において、金属層及び合成樹脂層を有するフィル
ム状の封止部材で、前記半導体素子および接続箇所を気
密封止したことを特徴とする半導体装置。A printed wiring board on which a conductive circuit pattern is formed, a semiconductor element fixed on the printed wiring board and connected to the circuit pattern, and a connection point between the semiconductor element, the semiconductor element, and the circuit pattern. What is claimed is: 1. A semiconductor device in which the semiconductor element and the connection portion are hermetically sealed with a film-like sealing member having a metal layer and a synthetic resin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61252976A JPS63107148A (en) | 1986-10-24 | 1986-10-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61252976A JPS63107148A (en) | 1986-10-24 | 1986-10-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63107148A true JPS63107148A (en) | 1988-05-12 |
Family
ID=17244770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61252976A Pending JPS63107148A (en) | 1986-10-24 | 1986-10-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107148A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089439A (en) * | 1990-02-02 | 1992-02-18 | Hughes Aircraft Company | Process for attaching large area silicon-backed chips to gold-coated surfaces |
-
1986
- 1986-10-24 JP JP61252976A patent/JPS63107148A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089439A (en) * | 1990-02-02 | 1992-02-18 | Hughes Aircraft Company | Process for attaching large area silicon-backed chips to gold-coated surfaces |
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