JPS63106841A - Debug device - Google Patents

Abstract

PURPOSE:To reference the content of a user side memory by supplying data read from the use memory to a 2nd microprocessor when an address signal corresponding to a prescribed address set in a memory reference control means is supplied from a 1st microprocessor during the execution of a user program. CONSTITUTION:When an address signal outputted from a slave microcomputer SMCU is coincident with an address corresponding to a control data CD having a level '1b set in a control memory CM in advance during the execution of the use program, the data read from a user memory UM or a substitution memory SM to a slave data bus SDB is latched by a latch circuit LAT. Thus, a master microcomputer MMCU bring a read control signal RC to a read level in a desired timing. Thus, the data of a prescribed address to be referenced in the substitution memory SM or the user memory UM is referenced without stopping the execution of the user program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique for referring to a user memory provided in an address space controlled by a debugging device, and furthermore, a microprocessor on the side of a device to be debugged. For example, it relates to techniques that are effective when applied to emulators.

[Prior art]

In the development of microcomputer application equipment, emulators can be used to debug the application system and provide detailed evaluation of the system. Such an emulator is connected between a system development device such as a parent computer for software development and an application device under development, and acts as a substitute for the functions of a microcomputer (target microcomputer) included in the application device. It is a microcomputer system development tool that functions as a debugger and supports detailed system debugging.

Conventional emulators include a slave microcomputer for emulation that performs the functions of a target microcomputer, as described in "■, SI Handbook", pages 562 and 563, published by Ohmsha on November 30, 1980. It also has a built-in emulation control section that implements emulation and various debugging functions, a breakpoint control section, a trace memory section, a substitute memory section, and a mask microcomputer for controlling these sections. .

In such an in-circuit emulator, the end of a cable extended from the main body is connected to a socket for a target microcomputer included in an application device, so that the slave microcomputer (1) can take over the functions of the target microcomputer. Equipped with emulation functions. Furthermore, various data and status signals are sampled during emulation,
It is equipped with various debugging functions, such as a trace function that stores the data in a trace memory, and a break function that stops the slave microcomputer from controlling the application equipment.

By the way, in order to improve debugging efficiency in the emulator, it is desirable to enable the mask microcomputer to appropriately refer to the contents of memory allocated to the application device side space, such as user memory and proxy memory. .

However, conventionally, such a read operation for memory reference is performed while the emulation operation, that is, the execution of the program on the application device side is temporarily stopped. For example, while a slave microcomputer is executing a program for application equipment, a wait state is created for the execution of the program at predetermined intervals, and at that time, the mask microcomputer is enabled to perform a memory read operation as required.

[Problem that the invention seeks to solve]

However, according to the studies of the present inventors, the technology that enables the mask microcomputer to perform memory read operations by creating a wait state during the execution of the emulation operation described above does not allow for strict control such as motor rotation control. For application equipment that requires program execution under time management, if the program execution is interrupted in such a waiting state, equipment such as servo motors that should be controlled by the program will be in the controlled state. It has been revealed that there is a risk that the police will escape and go out of control.

SUMMARY OF THE INVENTION An object of the present invention is to provide a debugging device that can appropriately refer to the contents of a user-side memory without stopping the execution of a user program during emulation operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief summary of typical inventions disclosed in this application is as follows.

That is, the control data can be set programmably under the control of the second microprocessor in correspondence with the address of the user side memory to be referenced by the second microprocessor that controls debugging, and memory reference control means capable of inputting an address signal output from the first microprocessor and outputting the control data while a user program is being executed by the first microprocessor that performs the functions of the microprocessor of the device to be used; The second microprocessor can selectively supply data read from the user side memory during execution of a user program to the second microprocessor based on control data output from the memory reference control means.

[For production]

According to the above-mentioned means, during the execution of the user program,
When an address signal corresponding to the address set in the memory reference control means is supplied from the first microprocessor, reading is performed from the user side memory based on control data output from the memory reference control means in response. By supplying the stored data to the second microprocessor, the contents of the user side memory can be referenced without stopping the execution of the user program during emulation operation.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a debugging device according to the present invention. The figure shows a configuration applied to an emulator, which is formed by a known semiconductor integrated circuit manufacturing technique, although it is not particularly limited.

The emulator IE shown in FIG. 1 performs the operation control, that is, emulation, of the microcomputer application equipment (hereinafter simply referred to as application equipment) AU, which is the user's actual machine, by acting on behalf of the target microcomputer included in the AU. It includes a slave microcomputer SMCU for performing debugging functions, and a master microcomputer MMCU for controlling various debugging functions. The slave microcomputer SMCU above
Due to the nature of proxy control, it has at least the same functionality as a target microcomputer (not shown), and is controlled by a cable CB that includes a slave data bus SDB, a sphere address bus SAB, and a slave control bus (not shown). Target microcomputer installation area ME of device AU
It is connected to the.

The application equipment AU is equipped with various devices depending on its system configuration, and these devices are controlled by a slave microcomputer SMCU operated based on a user program. In FIG. 1, one user memory UM of such devices is representatively shown. This user memory UM is RAM (
It is composed of a rewritable semiconductor memory device such as a random access memory (random access memory).

The application equipment AU that is connected to the emulator IE and is the target of system debugging and evaluation is still in the process of system development, so the application equipment AU that is under development has a sufficient number of user memories necessary for its operation. It may not be installed. Therefore, the emulator IE is provided with a proxy memory SM to compensate for the shortage of user memory so as to receive access control from the slave microcomputer SMCU. This proxy memory SM is also R
It is composed of a rewritable semiconductor memory device such as AM (Random Access Memory).

The emulator IE of this embodiment has an emulation function that takes over the functions of the target microcomputer, a trace function that samples various data and status signals during emulation execution, and stores them in a trace memory, and a slave microcomputer. Not only does it have various debugging functions that ordinary emulators have, such as a break function that stops the control operation of applied equipment by the SMCU, but it also allows the user program to be executed without stopping the execution of the user program during the emulation operation by the slave microcomputer SMCU. The mask microcomputer MMCU is configured to be able to refer to the contents of the user memory UM and proxy memory SM. In this embodiment, in order to achieve such a memory reference function, a mask microcomputer M is used.
Control data CI) in correspondence with predetermined addresses of the user memory UM and proxy memory SM that MCU should refer to.
can be set programmably based on the control of the mask microcomputer MMCU, and during execution of the user program by the slave microcomputer SMCTJ, the address output from the slave microcomputer SM, CTJ can be set programmably based on the control of the mask microcomputer MMCU. a memory reference control means MSC capable of inputting signals and outputting the control data CD; and the user memory UM and the substitute memory S.
Memory reference control means MSC for data read from M
A gate means GC is newly provided for selectively supplying control data CD to the mask microcomputer MCU based on the control data CD output from the control data CD.

The memory reference control means MSC may be an SRAM that stores 1-bit data in a rewritable manner, although it is not particularly limited.
It mainly uses control memory CM such as (static random access memory). According to this embodiment, the control memory CM is set with the same address as at least the address space of the user memory UM and the substitute memory SM, and has the same storage capacity as them. The address signal input terminal A in of the control memory CM receives an address signal supplied from the master microcomputer MMCU via the mask address bus MAB and from the slave microcomputer SMCU via the slave address bus SAB. The output terminal of the address multiplexer AMPX is connected to the output terminal of an address multiplexer AMPX that selectively outputs an address signal, and the output selection operation of the address multiplexer AMPX is controlled by a selection control signal SEL supplied from the master microcomputer MMCU
It is now carried out by A data input terminal of control memory CM is coupled to one signal line of master data bus MDB so as to receive predetermined 1-bit data from mask microcomputer MMCU.

The mask microcomputer MM CU resets all data stored in the control memory CM to level "0" in advance at a timing other than when the slave microcomputer SM CU is executing a user program, such as during an initialization reset or during a break. Later, the address multiplexer AMPX is controlled to be able to output the input signal from the mask address bus MAB, and the controller 1 to roll memory CM are controlled to be in a state where a write operation is possible. Then, the master microcomputer MM CU outputs an address signal corresponding to a predetermined address of the user memory UM or proxy memory SM to be referenced during the execution of the user program, and also outputs an address signal corresponding to a predetermined address of the user memory UM or substitute memory SM.
” control data CD is output.

As a result, the control memory CM has a level "1" in the memory cell corresponding to one address to be referenced.
control data CD is stored, and control data CD of level "O" is stored in subsequent memory cells.

The mask microcomputer MMCU uses the address multiplexer AMPX while the slave microcombicoater SMCU is executing the user program.
is controlled to be able to output the input signal from the slave AT1 NOS bus SAB, and control the control memory CM to be in a readable state. Therefore, while the user program is running, the slave micro combi coater S
When the address signal output from the MCU matches the address corresponding to the level "1" control data CD set in advance in the control 1-roll memory CM, that level "] is output from the data output terminal Dout of the control memory CM. -" control data CD is read out. At this time,
Data corresponding to the address signal is read from the user memory UM or the substitute memory SM onto the slave data bus S(D)B.

The gate means GC is, although not particularly limited, an input terminal coupled to the slave data bus SDR and a latch that latches input data when the control data CD supplied from the control memory CM is at level "1". The input terminal is coupled to the output terminals of the circuit LAT and the latch circuits T and AT, and the input signal can be output to the master data bus MDB based on the read control signal RC output from the mask microcomputer MCU. It is composed of an output buffer circuit BUF.

Therefore, when the address signal output from the slave microcomputer SMCU during execution of the user program matches the address corresponding to the control data CD of level "1" set in advance in the control memory CM, at this time, the corresponding address A signal is sent from the user memory UM or substitute memory SM to the slave data bus SD.
The data read to B is the control data C of level "1" output from the control memory CM at that time.
The signal is latched by the latch circuit LAT based on the signal D. As a result, by setting the read control signal RC to the read level at a desired timing, the master microcomputer MMCU can stop the execution of the user program by setting the data at the desired address to be referenced in the proxy memory SM or the user memory UM. You can refer to it without any problems.

In this case, since the data once latched in the latch circuit LAT is held until the contents of the control memory CM are rewritten, the mask microcomputer MM
The CU can refer to necessary data at any time until the execution of a series of user programs is stopped.

According to the above embodiment, the following effects can be obtained.

(1) During the execution of the user program, the address signal output from the slave microcomputer SMCU is set to the level "1" set in advance in the control memory CM.
” matches the address corresponding to the control data CD,
At this time, the user memory UM is
Alternatively, the data read from the proxy memory SM to the slave data bus SDB is latched by the latch circuit LAT based on the level "1" control data CD output from the control memory CM at that time, so that the mask microcomputer By setting the read control signal RC to the read level at a desired timing, the MMCU can refer to data at a predetermined address to be referenced in the proxy memory SM or user memory UM without stopping the execution of the user program. .

(2) The data once latched in the latch circuit LAT is
Since the contents of the control memory CM are retained unless rewritten, the mask microcomputer MMCU
can refer to necessary data at any time until execution of a series of user programs is stopped.

(3) From the above effect, the user can know how the contents of the user side memory such as the user memory UM and the proxy memory SM change during emulation operation without stopping the emulation operation. System operation can be dynamically monitored without sacrificing real-time performance in terms of program execution.

(4) As a result of the above effects, the efficiency of system debugging and system evaluation in the emulator can be significantly improved.

(5) Since the emulator IE of this embodiment has a configuration in which a memory reference control means MSC and a gate means GC are added to a normal emulator, the user only needs to consider the drivability of the slave bus and master bus. Each of the above effects can be obtained without any effect on program execution.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

For example, in the embodiment described above, both the user memory UM and the proxy memory SM are configured to be referenceable, but either one of them may be omitted. Further, in the above embodiment, the memory reference control means using 1-bit control data has been described, but the present invention is not limited to this, and the control data may also be a full-bit structure for the bit structure of the master data bus MDB. Often, by doing so, the number of data that can be referenced during execution of a series of user programs can be dramatically increased. Furthermore, the memory reference control means is not limited to a configuration mainly based on SRAM, but may also be configured mainly using an electrically rewritable programmable logic array, and furthermore, it may be configured mainly using an electrically rewritable programmable logic array. It can also be constructed by a latch circuit that latches an address signal output from the slave microcomputer, and a comparator 1 notor that determines whether the output of the latch circuit matches the address signal output from the slave microcomputer and outputs control data. Further, by providing a light emitting element such as an LED at the end of the latch circuit LAT of the above embodiment, it is possible to visually confirm that the data to be referenced has been read out to the latch circuit.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to emulators, which is the field of application that formed the background of the invention, but it is not limited to this, and other applications for the purpose of system debugging and system evaluation. It can be widely applied to various debugging devices. The present invention can be applied to a device having at least a first microprocessor that performs the functions of a microprocessor of a device to be debugged, and a second microprocessor that controls debugging.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, the control data can be programmably set under the control of the second microprocessor in correspondence with a predetermined address of the user side memory to be referenced by the second microprocessor that controls debugging, and User programmer 1 using a first microprocessor that performs the functions of a microprocessor in a device that is said to be
1, a memory reference control means capable of outputting the control data by inputting the address signal output from the first microprocessor is provided, and the memory reference control means is capable of outputting the control data from the user side memory during the execution of the user program. Since the data to be read can be selectively supplied to the second microprocessor based on the control data output from the memory reference control means, the read data can be selectively supplied to the second microprocessor based on the control data output from the memory reference control means. When a corresponding address signal is supplied from the first microprocessor, data read from the user side memory can be supplied to the second microprocessor based on control data output from the memory reference control means in response. By doing so, the contents of the user side memory can be referenced without stopping the execution of the user program during emulation operation.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of a debugging device according to the present invention. MMCU --- Mask microcomputer, SMCU
...Slave microcomputer, UM...User memory, SM...Deputy memory, MSC...Memory reference control means, AMPX...Address multiplexer, CM...Control memory, GC... - Gate means, LAT...latch circuit, BUF...output buffer circuit, CD...control data. TE A'0

Claims (1)

[Scope of Claims] 1. A debugging device comprising a first microprocessor that performs the functions of a microprocessor of a device to be debugged, and a second microprocessor that controls debugging, the debugging device comprising: a rewritable memory provided in an address space under the jurisdiction of the microprocessor, and an address of the memory to be referenced by the second microprocessor that can be programmably set based on control of the second microprocessor; memory reference control means capable of comparing an address signal outputted from the first microprocessor with the set address during execution of a program by the first microprocessor and outputting control data according to the result; and gate means for selectively supplying data to the second microprocessor based on control data output from the memory reference control means. 2. The memory reference control means inputs address signals supplied from the first and second microprocessors via a multiplexer selectively controlled by the second microprocessor, and receives address signals from the second microprocessor accordingly. A random controller that inputs the supplied control data and outputs the control data to the gate means.
2. The debug device according to claim 1, wherein the debug device is an access memory. 3. The gate means includes a latch circuit that latches read data from the memory based on control data supplied from the memory reference control means, and a latch circuit that latches the data latched in the latch circuit based on the control of the second microprocessor. 3. The debug device according to claim 1, further comprising an output buffer circuit that can be supplied to a microprocessor.