JP3833897B2 - Control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device that can be used for various devices such as machine tools and is effective for cost reduction and downsizing.
[0002]
[Prior art]
A general control device using a microcomputer includes a CPU, a ROM that is a storage device that stores a program to be executed by the CPU, and a RAM that is a storage device that stores variables necessary for the execution of the program. In addition, it is composed of necessary circuits and the like and realizes its function.
If the control contents are simple, it is sufficient to have one CPU, one ROM, one RAM, etc., but if the control contents are complicated or the processing speed is required to be increased, a plurality of units are provided. A program is distributed and processed, or a dedicated processing unit is provided for each function.
For example, when a program is distributed and executed by a plurality of CPUs, each unit basically performs a single operation independently, and transmission of data necessary between the units is made up of a shared RAM or the like. The interface is used to increase the speed and functionality of the entire control device.
[0003]
By the way, in the conventional control device, as shown in FIG. 4, ROM and RAM are provided for each CPU of each unit, and when the power is turned on, the CPU of each unit is dedicated from the ROM provided for each CPU. It was supposed to read and execute the program and perform the operation. For this reason, the conventional control device requires at least as many ROMs as the number of CPUs.
[0004]
[Problems to be solved by the invention]
However, as the performance of the control device increases and the number of units increases, the number of mounted chips increases and a larger mounting area is required, making it difficult to reduce the size of the control device. In the case of ROM, since writing work for each ROM is required, the number of man-hours increases as the number of ROMs increases.
In general, since a ROM having a larger capacity than the program capacity to be written is selected and used, when a ROM is provided for each CPU as in the prior art, there are many ROMs while leaving an unused area. It was also inefficient.
Further, even when the same program is operated by a plurality of CPUs, a ROM in which the same program is written has to be mounted for each CPU. In particular, when the program is a large program having a plurality of operations, it is very inefficient to write the same program in each ROM and mount each ROM.
In addition, since the control device has a different program to be written in the ROM for each model, the management man-hour increases as the number of ROM types increases.
The present invention has been made in view of such circumstances. In other words, at least one of the following: writing man-hours and time for writing programs to the ROM, reducing device costs, chip mounting man-hours and mounting area, downsizing the control device, and reducing model ROM management man-hours required for each model It is an object of the present invention to provide a control device that can achieve this.
[0005]
[Means for Solving the Problems]
Therefore, the present inventor has eagerly studied to solve this problem, and as a result of repeated trial and error, has come up with the idea of deleting the lower ROM in the control device composed of a plurality of units, and develops the control device of the present invention. Has been reached.
That is, the control device according to the present invention includes an upper unit composed of an upper CPU, an upper RAM capable of reading and writing data by the upper CPU, and an upper ROM from which data can be read by the upper CPU, and data by the lower CPU and the lower CPU. A plurality of lower units that are not provided with a ROM dedicated to the lower CPU, and are provided between the upper unit and the lower unit. A readable / writable shared RAM, a lower unit transfer program for transferring a program stored in the shared RAM to the lower RAM, and a plurality of lower unit system programs selected according to the operation mode of the upper unit A program for a lower unit executable by at least the lower CPU including the upper CPU Further comprising a transfer means for transferring from the ROM to the shared RAM, and activation control means for causing starting the lower position CPU after said transfer means has finished transferring the transfer program for lower level units from said upper ROM to the shared RAM, and It is characterized by.
[0006]
The control device according to the present invention is such that the conventional concept that a ROM is required for each CPU is reversed, and the ROM on the lower unit side is deleted. Then, when deleting the ROM, the lower unit programs conventionally stored in the ROM are collectively stored in the upper ROM in the present invention, and are shared between the upper unit and the lower unit. The RAM is used effectively, and the lower unit program is transferred from the upper ROM to the shared RAM by the transfer means so that the lower CPU can execute the lower unit program.
However, in order for the lower CPU to execute the lower unit program, first, it is assumed that the program to be executed is transferred to at least the shared RAM. Therefore, it is necessary to control the start timing of the lower CPU. . Therefore, the start control means performs this start control.
The transfer means is, for example, an upper transfer program executed by the upper CPU.
[0007]
A plurality of lower unit system programs are stored in the upper ROM, and the upper transfer program includes a program for transferring the lower unit system program selected according to the operation mode of the upper unit. Yes.
Since the necessary operation mode of the lower unit is determined according to the operation mode of the upper unit, if only the lower unit system program necessary for the operation of the lower unit can be transferred, the transfer time can be shortened and the shared RAM can be transferred. In addition, it is possible to effectively use the lower RAM or reduce the capacity.
[0008]
Further, the activation control means is, for example, a reset release signal output from the upper CPU to the lower CPU.
The lower CPU is started after the lower unit program necessary for the operation of the lower unit is transferred from the upper ROM to the shared RAM, and the upper CPU executing the transfer outputs a reset release signal. And output of abnormal signals can be prevented.
[0009]
Incidentally, the reason why the lower unit program includes at least the lower unit transfer program is as follows.
If the entire lower unit program to be transferred has a small capacity, the lower CPU can directly read and execute the program transferred to the shared RAM from the shared RAM. However, if the capacity of the lower unit program is large or consists of programs having multiple functions, the necessary program (for example, the lower unit system program) is transferred to the lower RAM according to the situation, and then the lower unit It is preferable from the viewpoint of processing speed or the like that the CPU reads and executes the program in its lower RAM. In this case, a lower unit transfer program for transferring data from the shared RAM to the lower RAM is required, and the lower CPU executes the lower unit transfer program transferred from the upper ROM to the shared RAM in advance. That is, at this time, the lower CPU starts reading the lower unit transfer program (data) from a predetermined address of the shared RAM in which the lower unit transfer program is stored at the same time of activation.
[0010]
Note that the above-mentioned “upper” and “lower” are names for convenience, and do not indicate upper or lower of the function of the entire control apparatus. Needless to say, the CPU is a central processing unit, which includes various commonly used CPUs, and may include a cache. The RAM is usually a volatile memory that can be temporarily stored, and includes a DRAM and an SRAM. The shared RAM is composed of a dual port (2-port) RAM, etc., which can be read and written from both ports, and can exchange data between both units. The ROM is a non-volatile memory and includes a mask ROM, a PROM (EPROM, EEPROM, flash memory, etc.), and the like.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Next, the control device of the present invention will be described more specifically with reference to an embodiment.
First, the concept of the present invention will be described in detail with reference to FIGS. FIG. 1 schematically shows a main part according to the present invention in a circuit configuration arranged on a control board of a control device (for example, an NC device of a machine tool). In FIG. 1, only two units, the upper unit and the lower unit, are shown for ease of understanding. However, even if there are a plurality of lower units or a combination of the upper unit and the lower unit, Basically the same.
[0012]
Both the upper unit 10 and the lower unit 20 shown in FIG. 1 are connected to the external devices 15 and 25 via the interfaces (I / F) 14 and 24, and output signals and data to the external devices 15 and 25. The external device can be controlled, and signals and data can be received from the external devices 15 and 25.
A shared RAM (2-port RAM) 30 serving as an interface between the upper unit 10 and the lower unit 20 is provided. By using this shared RAM 30 as a buffer, data and signals can be transmitted and received and programs can be transferred between the upper unit 10 and the lower unit 20.
[0013]
By the way, as apparent from comparison between FIG. 1 showing the control device according to the present invention and FIG. 4 showing the conventional control device, the ROM on the lower unit 20 side is omitted in the control device according to the present invention. ing.
The operation of the control device shown in FIG. 1 will be described with reference to FIG. FIG. 2 schematically shows a program hierarchically stored in a ROM (upper ROM) 13 composed of a flash memory provided on the upper unit 10 side.
[0014]
(1) The upper CPU 11 is configured to start when reset is released by an output signal from a power supply monitoring circuit (not shown). When the upper CPU 11 is activated, the upper unit program is read from the ROM 13 and starts executing. Further, the host CPU 11 accesses the RAM 12 as necessary to temporarily store programs and data.
[0015]
(2) Next, the upper CPU 11 executes the transfer program (upper transfer program) included in the above-mentioned upper unit program (transfer means), and executes a lower unit transfer program which is a kind of lower unit program. Transfer from the ROM 12 to the shared RAM 30.
[0016]
(3) Next, the upper CPU 11 receives the transfer completion signal and outputs a reset release signal to the lower CPU 21 (startup control means).
[0017]
(4) The lower CPU 21 is activated in response to the reset release signal, reads the lower unit transfer program already transferred to the shared RAM 30, and starts executing it. The lower CPU 21 is configured to read data from a predetermined address in the shared RAM 30 at the time of activation.
Thus, the lower CPU 21 can transfer the program transferred from the ROM 13 to the shared RAM 30 to the RAM 22 on the lower unit 20 side.
[0018]
(5) Next, the upper CPU 11 executes the above-described upper transfer program again, and transfers the lower unit system program (1) stored in the lower layer of the lower unit transfer program in the ROM 13 to the shared RAM 30.
However, depending on the operation mode of the upper unit 10, the lower unit system program (2) may be transferred to the shared RAM 30. Further, even during the transfer of the lower unit system program {circle around (1)}, it may be switched to the lower unit system program {circle around (2)}.
[0019]
(6) Waiting for the completion of the transfer process of the program from the upper CPU 11 to the shared RAM 30, or in parallel with the transfer process, the lower CPU 21 sequentially loads the lower unit system program (1) transferred to the shared RAM 30. Transfer to the RAM 22 is started.
[0020]
(7) When the transfer to the RAM 22 is completed, the lower CPU 21 reads and executes the lower unit system program transferred from the RAM 22 and exhibits the functions of the lower unit 20.
In this way, the control device of the present invention effectively uses the ROM and shared RAM on the upper unit side while reducing the ROM on the lower unit side, and is cost-effective without any functional inferiority to the conventional control device. We have succeeded in reducing the mounting area of the board or downsizing the control device.
[0021]
In the above description, the case where the lower CPU 21 executes the program after the transfer of the lower unit system program to the RAM 22 has been described. However, the upper CPU may change during transfer or execution. It is also possible to change the operation of the lower CPU by transferring the lower unit system program again.
Also, if there are multiple lower units and each lower CPU operates with the same program, program sharing (that is, consolidate the programs stored in the upper ROM into one) and the same program from the upper ROM to each lower You may make it transfer to RAM and each shared RAM.
[0022]
Next, an NC apparatus 100 for a machine tool according to an embodiment of the present invention is shown in FIG. In FIG. 3, the main part of the control board according to the present invention is mainly shown.
As in the control device shown in FIG. 1, the NC device 100 includes a host CPU 111, a host RAM 112, and a host ROM 113 including a flash memory. The contents of the program stored in the upper ROM 113 are basically the same as those shown in FIG.
[0023]
The host CPU 111 can communicate with an external device connected to the connector 115 via the interface (I / F) 114 and also controls a PLC (programmable logic controller) connected to the connector 165. 160 can also be input / output.
On the other hand, the servo control unit is exemplified as the lower unit. The servo control unit includes a first servo amplifier unit (first lower unit) that controls the first servo and a second servo amplifier unit (second lower unit) that controls the second servo.
[0024]
The first servo amplifier section includes a lower CPU 121, a first servo interface (I / F) 124, and a RAM 122, and is connected to the first servo via a connector 125. A shared RAM 130 is provided between the upper units.
[0025]
The second servo amplifier section includes a lower CPU 141 and a second servo interface (I / F) 144 and is connected to the second servo via the connector 145. A shared RAM 150 is provided between the upper units.
Therefore, this NC apparatus 100 corresponds to the case where there are two lower units for one upper unit. The upper ROM 113 stores the lower unit system program and the lower unit transfer program necessary for realizing the functions of the first servo amplifier unit and the second servo amplifier unit together with the upper unit program. ing.
[0026]
By the way, in the case of the NC apparatus 100 shown in FIG. 3, the RAM 122 is provided in the first servo amplifier unit, whereas the dedicated servo RAM is not provided in the second servo amplifier unit, and the shared RAM 150 is also used. It was decided. Therefore, the “lower RAM” in the present invention can be considered to be included in the “shared RAM”. In other words, the lower-level RAM referred to in the present invention does not necessarily have to exist independently.
[0027]
Also, the wavy arrow shown in FIG. 3 shows the flow of program transfer. That is, necessary data (program) is written in the upper ROM 113 by the ROM writer before or after mounting on the board. Of the written programs, the programs executed by the lower CPU 121 or the lower CPU 141 are transferred to the shared RAM 130 or the shared RAM 150, respectively.
[0028]
In FIG. 3, only the main part according to the present invention is shown, but a large number of chips and units are integrated and incorporated in a control board constituting an actual NC apparatus. For this reason, it has been difficult to increase the number of chips and the like in the conventional control board as the functions increase, but according to the present invention, it is possible to mount other chips and units as much as the ROM can be reduced. Further, it is possible to achieve further enhancement of the function of the control device while avoiding an increase in the size of the control device.
[0029]
【The invention's effect】
According to the control device of the present invention, even if the number of units increases, the ROM of the lower unit can be reduced. Therefore, the number of steps for writing programs to the ROM, the writing time, the device cost, the chip mounting man-hours can be reduced. Cost reduction associated with reduction or reduction in the number of man-hours for managing the model ROM, and downsizing of the control device associated with reduction in mounting area, etc. can be achieved.
[Brief description of the drawings]
FIG. 1 is a schematic diagram conceptually showing a control device according to the present invention.
FIG. 2 is an explanatory diagram hierarchically showing programs stored in a host ROM used in the control device according to the present invention.
FIG. 3 is a diagram showing a main part of a control board of the NC apparatus according to the embodiment of the present invention.
FIG. 4 is a schematic diagram conceptually showing a conventional control device.
[Explanation of symbols]
11, 111 Host CPU
13, 113 (Upper) ROM
12, 112 (upper) RAM
21, 121, 141 Lower CPU
22, 122 (lower) RAM
30, 130, 150 Shared RAM
100 NC unit (control unit)

Claims (3)

A host unit comprising a host CPU, a host RAM capable of reading and writing data by the host CPU, and a host ROM capable of reading data by the host CPU;
A plurality of subordinate units, each comprising a subordinate CPU and a subordinate RAM capable of reading and writing data by the subordinate CPU, and not provided with a ROM dedicated to the subordinate CPU;
A shared RAM provided between the upper unit and the lower unit and capable of reading and writing data by the upper CPU and the lower CPU;
Executed by the lower CPU including at least a lower unit transfer program for transferring a program stored in the shared RAM to the lower RAM and a plurality of lower unit system programs selected according to the operation mode of the upper unit Transfer means for transferring possible lower unit programs from the upper ROM to the shared RAM;
And activation control means for causing starting the lower position CPU after said transfer means has finished transferred to the shared RAM transfer program 1026 the subordinate unit from said upper ROM,
A control device comprising: The control device according to claim 1, wherein the transfer unit is a higher-level transfer program executed by the higher-level CPU. The control device according to claim 1, wherein the activation control means is a reset release signal output from the upper CPU to the lower CPU.

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