JPS631067A - Charge coupled device - Google Patents
Charge coupled deviceInfo
- Publication number
- JPS631067A JPS631067A JP61145335A JP14533586A JPS631067A JP S631067 A JPS631067 A JP S631067A JP 61145335 A JP61145335 A JP 61145335A JP 14533586 A JP14533586 A JP 14533586A JP S631067 A JPS631067 A JP S631067A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- coupled device
- conductivity type
- charge
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 33
- 229910052710 silicon Inorganic materials 0.000 description 33
- 239000010703 silicon Substances 0.000 description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000003384 imaging method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Filters That Use Time-Delay Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は固体撮像素子の信号電荷転送、遅延回路および
記憶用電子テパイスなどに用いることができる電荷結合
素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a charge-coupled device that can be used in signal charge transfer of solid-state image pickup devices, delay circuits, storage electronic devices, and the like.
従来の技術
近年、電荷結合素子はｐ形シリコン基板上にｎ形シリコ
ン層を形成し、ｎ形シリコン層に酸化シリコン層を介し
てパルス電圧を印加して埋め込みチャンネルを形成する
ＭＯ９Ｏ９容量次元または２次元的に配列したものが用
いられている。Prior art In recent years, charge-coupled devices have been developed by forming an n-type silicon layer on a p-type silicon substrate, and applying a pulse voltage to the n-type silicon layer through a silicon oxide layer to form a buried channel. A dimensional array is used.
以下図面を参照しながら上述したような従来の電荷結合
素子を説明する。第５図は従来の埋め込みチャンネルの
電荷結合素子の構成図である。The conventional charge coupled device as described above will be explained below with reference to the drawings. FIG. 5 is a block diagram of a conventional buried channel charge coupled device.
ｐ形シリコン基板６上にイオン注入などの方法を用いて
ｎ形シリコン層４を形成し、酸化シリコン層２を介して
、パルス電圧を印加する多結晶シリコン層１．３を形成
する。多結晶シリコン層１゜３は、互いに酸化シリコン
層によって絶縁されている。An n-type silicon layer 4 is formed on a p-type silicon substrate 6 using a method such as ion implantation, and a polycrystalline silicon layer 1.3 to which a pulse voltage is applied is formed via a silicon oxide layer 2. The polycrystalline silicon layers 1.3 are insulated from each other by a silicon oxide layer.
多結晶シリコン層、酸化シリコン層、ｎ形シリコン層と
ｐ形シリコン層から形成されているＭＩＳ（金属−絶縁
層一半導体構造）容量を２つ以上釜べて形成し、隣り合
うＭＩＳ容量の空乏領域が重なるように構成しである。Two or more MIS (metal-insulating layer-semiconductor structure) capacitors formed from a polycrystalline silicon layer, a silicon oxide layer, an n-type silicon layer, and a p-type silicon layer are formed together, and the depletion of adjacent MIS capacitors is eliminated. The configuration is such that the areas overlap.
多結晶シリコン層にパルス電圧を順次加えることにより
ＭＯ３容量に蓄積されている電荷を順次隣りのＭＯ８容
量に転送する。By sequentially applying pulse voltages to the polycrystalline silicon layer, the charges accumulated in the MO3 capacitor are sequentially transferred to the adjacent MO8 capacitor.
発明が解決しようとする問題点
しかしながら、上記のような構成ではパルス電圧とｎ形
シリコン層４の不純物濃度そしてＭＩＳ容量の面積に依
存し、電荷結合素子として動作させるには、パルス電圧
とｎ形不純物層４の不純物濃度に制限があるためにＭＩ
Ｓ容量の面積を小さくするとＭＯ３容量が小さくなシミ
荷結合素子の取り扱い電荷量が少なくなることになる。Problems to be Solved by the Invention However, the above configuration depends on the pulse voltage, the impurity concentration of the n-type silicon layer 4, and the area of the MIS capacitor. Because there is a limit to the impurity concentration of impurity layer 4, MI
If the area of the S capacitor is reduced, the amount of charge handled by the stain coupling element with a small MO3 capacitance will be reduced.
例えばＣＯＤ固体撮像素子においては、画素寸法が小さ
くなると垂直転送の電荷結合素子の取り扱い電荷量が少
なくなり、信号のダイナミックレンジが少さくなるとい
うことが起きてくる。For example, in a COD solid-state image sensor, as the pixel size becomes smaller, the amount of charge handled by the vertical transfer charge-coupled device becomes smaller, and the dynamic range of the signal becomes smaller.
本発明は上記欠点に鑑み、小面積においても取り扱い電
荷量が減少しない構成の電荷結合素子を提供するもので
ある。In view of the above drawbacks, the present invention provides a charge-coupled device having a structure in which the amount of charge handled does not decrease even in a small area.
問題点を解決するための手段
上記問題点を解決するために本発明の電荷結合素子は、
−導電型半導体基板、上に部分的に反対導電型半導体層
が形成され絶縁膜を介して電極が形成されて構成されて
いる。Means for Solving the Problems In order to solve the above problems, the charge coupled device of the present invention includes:
- A semiconductor substrate of a conductivity type, a semiconductor layer of an opposite conductivity type is partially formed on the substrate, and an electrode is formed with an insulating film interposed therebetween.
作 用
この構成によって、反対導電型半導体層の幅が小さくな
っても、高さを高くすることによって上記−導電型半導
体層上の単位面積当たりのＭＩＳ容量が従来に比べて大
容量とすることができ、電荷結合素子の高集積化に伴な
う取り扱い電荷量の減少を抑制できる。Effect: With this configuration, even if the width of the opposite conductivity type semiconductor layer is reduced, the MIS capacity per unit area on the above-mentioned conductivity type semiconductor layer can be increased compared to the conventional one by increasing the height. This makes it possible to suppress the decrease in the amount of charge handled due to the increase in the degree of integration of charge-coupled devices.
実施例
以下、本発明の一実施例について図面を参照しながら説
明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明の電荷結合素子の基本的構成例を示すも
のであシ、−導電型半導体基板１０上に部分的に反対導
電型半導体層８が形成され、絶縁膜９を介してパルス電
圧を印加する電極６，７が形成されている。反対導電型
半導体層８はパルス電圧印加で空乏化して電荷結合素子
のチャンネルを形成する。このチャンネルを通して信号
電荷を転送する。反対導電型半導体層８は選択エピタキ
シャル成長させるか、または、−導電型半導体層１ｏ上
全体にエピタキシャル成長させ、必要以外の部分をエツ
チング除去して形成する。反対導電型半導体層８の不純
物は、 °
゛ エピタキシャル成長時に同時に
混入させるか、またはエピタキシャル成長後にイオン注
入、または熱拡散で反対導電型半導体層８に入れる。FIG. 1 shows an example of the basic configuration of a charge-coupled device according to the present invention. Electrodes 6 and 7 for applying voltage are formed. The opposite conductivity type semiconductor layer 8 is depleted by applying a pulse voltage to form a channel of a charge coupled device. Signal charges are transferred through this channel. The opposite conductivity type semiconductor layer 8 is formed by selective epitaxial growth, or by epitaxial growth over the entire -conductivity type semiconductor layer 1o, and removing unnecessary portions by etching. Impurities in the opposite conductivity type semiconductor layer 8 are mixed simultaneously during epitaxial growth, or are introduced into the opposite conductivity type semiconductor layer 8 by ion implantation or thermal diffusion after epitaxial growth.
第２図は本発明の一実施例における電荷結合素子を用い
た固体撮像装置のより具体的な断面構成図を示すもので
ある。ｎ形シリコン層１３が電荷結合素子のチャンネル
となる部分である。ｎ形シリコン層１６は、ｎ形シリコ
ン層１５とｐ形シリは、信号電子を電荷結合素子チャン
ネルに読み出す多結晶シリコン電極である。またこの電
極１９及び電極１２にパルス電圧を順次印加し、読み出
した信号電子を転送する。１４は電極間の層間絶縁膜と
しての酸化シリコン層である。１６はＭＩＳ容量の酸化
シリコン層である。１１は遮光用のアルミニウムである
。１７はＰウェルであυ、１８はｎ形シリコン基板であ
る。ｎ形半導体層１５、Ｐウェル１７、ｎ形シリコン基
板１８によって縦型オーバーフロードレインが構成され
ている。FIG. 2 shows a more specific cross-sectional configuration diagram of a solid-state imaging device using a charge-coupled device according to an embodiment of the present invention. The n-type silicon layer 13 is a portion that becomes a channel of a charge coupled device. The n-type silicon layer 16, the n-type silicon layer 15, and the p-type silicon layer are polycrystalline silicon electrodes that read signal electrons into the charge-coupled device channel. Further, a pulse voltage is sequentially applied to the electrode 19 and the electrode 12 to transfer read signal electrons. 14 is a silicon oxide layer serving as an interlayer insulating film between electrodes. 16 is a silicon oxide layer of MIS capacitor. 11 is aluminum for light shielding. 17 is a P-well υ, and 18 is an n-type silicon substrate. The n-type semiconductor layer 15, the P-well 17, and the n-type silicon substrate 18 constitute a vertical overflow drain.
上記構成の製造方法の１つの方法を、第３図に示す。ｎ
形シリコン基板２ｏ上に数μｍ厚のｐ形シリコン層２１
を形成した後、ｐ形シリコン層２１上全体に酸化シリコ
ン層２２をＣＶＤで積層する。One method of manufacturing the above structure is shown in FIG. n
A p-type silicon layer 21 with a thickness of several μm is formed on a silicon substrate 2o.
After forming, a silicon oxide layer 22 is deposited over the entire p-type silicon layer 21 by CVD.
酸化シリコン層２２のうち電荷結合素子のチャンネルと
なる部分を選択的にエツチングする。次に気相エピタキ
シャル成長法でエツチング部分にｎ型シリコンを結晶成
長させる。その後、酸化シリコン膜２２を除去する。そ
の後の製造プロセスは、従来の電荷結合素子を用いた固
体撮像装置の製造プロセスと同じ方法を用いる。例えば
層間絶縁膜となる酸化シリコン１４は、減圧ＣＶＤで形
成する。多結晶シリコン電極１２．１９は、減圧ＣＶＤ
で形成する。遮光用アルミニウムは、減圧ＣＶＤで形成
する。A portion of the silicon oxide layer 22 that will become a channel of a charge coupled device is selectively etched. Next, crystals of n-type silicon are grown in the etched portions by vapor phase epitaxial growth. Thereafter, the silicon oxide film 22 is removed. The subsequent manufacturing process uses the same method as that of a conventional solid-state imaging device using a charge-coupled device. For example, the silicon oxide 14 which becomes an interlayer insulating film is formed by low pressure CVD. Polycrystalline silicon electrodes 12.19 are made by low pressure CVD.
to form. The light shielding aluminum is formed by low pressure CVD.
上記第２図の構成の製造方法の２番目の方法を第４図に
示す。ｎ形シリコン基板２６上にｐ形シリコン層２６及
びｎ形シリコン層２４をエピタキシャル成長法で結晶成
長させる。次にｎ形シリコン層２４を電荷結合素子のチ
ャンネル部以外を反応性イオンエツチングで選択エツチ
ングをして第４図の下図となる。後のプロセスは、従来
の電荷結合素子を用いた固体撮像装置の製造プロセスを
用いて行なう。A second method of manufacturing the structure shown in FIG. 2 is shown in FIG. A p-type silicon layer 26 and an n-type silicon layer 24 are crystal-grown on an n-type silicon substrate 26 by epitaxial growth. Next, the n-type silicon layer 24 is selectively etched by reactive ion etching except for the channel portion of the charge-coupled device, resulting in the result shown in the lower part of FIG. The subsequent process is performed using a conventional manufacturing process for a solid-state imaging device using a charge-coupled device.
本実施例では１４．１６を酸化シリコンとしたが、絶縁
物ならなんでもよく、例えば、窒化シリコンでもよい。In this embodiment, silicon oxide is used as 14.16, but any insulating material may be used, for example, silicon nitride may be used.
また本実施例では転送電極１２゜１９の材料を多結晶シ
リコンとしたが、導電材料ならなんでもよく例えばアル
ミニウムでもよい。Further, in this embodiment, the material of the transfer electrodes 12 and 19 is polycrystalline silicon, but any conductive material may be used, such as aluminum.
また本実施例では遮光膜１１をアルミニウムとしたが、
遮光材料であれば何でもよく例えば、タングステンでも
よい。また本実施例では、半導体材料を７リコンとした
が、ひ化ガリウム、インジウムリンなどの化合物半導体
でもよい。また本実施例では、突出したｎ形シリコン層
１３の形状を第２図で長方形としたが、多角形ならなん
でもよく三角形でもよい。Further, in this embodiment, the light shielding film 11 is made of aluminum, but
Any light blocking material may be used, for example, tungsten. Further, in this embodiment, the semiconductor material is 7 Licon, but a compound semiconductor such as gallium arsenide or indium phosphide may be used. Further, in this embodiment, the protruding n-type silicon layer 13 has a rectangular shape in FIG. 2, but it may be any polygonal shape or a triangular shape.
発明の効果
以上のように本発明は電荷結合素子のチャンネル部を半
導体基板上の部分的に半導体層に形成しその厚さを制御
することにより転送可能な信号量を増やすことができ、
高集積化に伴なう電荷結合素子の転送可能な信号量の減
少を抑制し、その実用的効果は大きなものがある。また
固体撮像装置に応用した場合、チャンネルが光電変換部
から空間的に離れる構成になるのでスミア現象が抑制で
きる。Effects of the Invention As described above, the present invention can increase the amount of signals that can be transferred by forming the channel portion of a charge-coupled device in a semiconductor layer partially on a semiconductor substrate and controlling its thickness.
This suppresses the decrease in the amount of signals that can be transferred by charge-coupled devices due to higher integration, and has a great practical effect. Furthermore, when applied to a solid-state imaging device, the channel is configured to be spatially separated from the photoelectric conversion section, so that smear phenomenon can be suppressed.
第１図は本発明の電荷結合素子の基本的な構成図、第２
図は本発明の一実施例の電荷結合素子を用いた固体撮像
装置の断面図、第３図、第４図は実施例の製造方法の一
部を示す断面図、第５図は従来の電荷結合素子の構成図
である。
１．３・・・・・・多結晶ケイ素電極、２・・・・・・
層間絶縁膜、４・・・・・・ｎ形半導体層、５・・・・
・・ｐ形半導体層、６．７・・・・・転送電極、８・・
・・・反対導電型半導体層、９・−・・−・層間絶縁膜
、１ｏ・・−・・・−導電型半導体層、１１・・・・・
・遮光用アルミニウム、１２・・・・・読み出し及び転
送電極、１３・・・・・・ｎ形シリコン層、１４゜１６
．１９・・・・・・酸化シリコン層、１５・・・・・・
ｎ形シリコン、１７・・・・・Ｐウェル、１８・・・・
・・ｎ 形シリ＝ｒン基板、２Ｑ・−・・・−ｎ形シリ
コン基板、２１・・・・・・ｐ形シリコン層、２２・・
・・・・酸化シリコン層、２３・・・・・・ｎ形シリコ
ン層、２４・・−・・・ｎ形シリコン層、２６・・・・
・ｐ形シリコン層、２６・・・・・ｎ形シリコン基板。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
乙
第２図
第３図Figure 1 is a basic configuration diagram of the charge coupled device of the present invention, Figure 2
The figure is a sectional view of a solid-state imaging device using a charge-coupled device according to an embodiment of the present invention, FIGS. 3 and 4 are sectional views showing a part of the manufacturing method of the embodiment, and FIG. FIG. 3 is a configuration diagram of a coupling element. 1.3...Polycrystalline silicon electrode, 2...
Interlayer insulating film, 4... n-type semiconductor layer, 5...
...p-type semiconductor layer, 6.7...transfer electrode, 8...
...Opposite conductivity type semiconductor layer, 9.--Interlayer insulating film, 1o...-conductivity type semiconductor layer, 11...
・Light-shielding aluminum, 12...readout and transfer electrode, 13...n-type silicon layer, 14゜16
．． 19...Silicon oxide layer, 15...
N-type silicon, 17...P well, 18...
... n-type silicon=r silicon substrate, 2Q...-n-type silicon substrate, 21...p-type silicon layer, 22...
...Silicon oxide layer, 23...N-type silicon layer, 24...N-type silicon layer, 26...
・P-type silicon layer, 26...n-type silicon substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure Otsu Figure 2 Figure 3
Claims (2)
層が形成され、この半導体層の上に絶縁層を介して導電
性膜が形成されていることを特徴とする電荷結合素子。(1) A charge-coupled device characterized in that a partially protruding semiconductor layer is formed on a semiconductor substrate of one conductivity type, and a conductive film is formed on this semiconductor layer with an insulating layer interposed therebetween.
と反対導電型であることを特徴とする特許請求の範囲第
１項記載の電荷結合素子。(2) The charge-coupled device according to claim 1, wherein the partially formed protruding semiconductor layer has a conductivity type opposite to that of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61145335A JPS631067A (en) | 1986-06-20 | 1986-06-20 | Charge coupled device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61145335A JPS631067A (en) | 1986-06-20 | 1986-06-20 | Charge coupled device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS631067A true JPS631067A (en) | 1988-01-06 |
Family
ID=15382791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61145335A Pending JPS631067A (en) | 1986-06-20 | 1986-06-20 | Charge coupled device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS631067A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03285335A (en) * | 1990-04-02 | 1991-12-16 | Matsushita Electron Corp | Charged transfer element and manufacture thereof |
| JP2013038161A (en) * | 2011-08-05 | 2013-02-21 | Toshiba Corp | Optical coupling device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55121678A (en) * | 1979-03-14 | 1980-09-18 | Pioneer Electronic Corp | Charge transfer device |
-
1986
- 1986-06-20 JP JP61145335A patent/JPS631067A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55121678A (en) * | 1979-03-14 | 1980-09-18 | Pioneer Electronic Corp | Charge transfer device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03285335A (en) * | 1990-04-02 | 1991-12-16 | Matsushita Electron Corp | Charged transfer element and manufacture thereof |
| JP2013038161A (en) * | 2011-08-05 | 2013-02-21 | Toshiba Corp | Optical coupling device |
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