JPS63106791A - Image display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multi-window image display device. The present invention relates to an image display device that can display multiple areas simultaneously.

(Prior Art) Conventionally known image display devices (color graphic displays) generally have a fixed display resolution and a fixed number of simultaneously displayed colors.

Generally, natural images, such as those input by a TV camera, do not need to have very high resolution, but require a large number of display colors. On the other hand, images such as characters and drawings output by CAD etc. do not require a large number of display colors, but require high resolution.

In an image display device used in a workstation or the like, there are cases where it is desired to simultaneously display characters, drawings, etc. along with natural images in a multi-window format. Conventionally,
In such cases, expensive image display devices with high resolution and multicolor display have been prepared.

(Problems to be Solved by the Invention) The present invention has been made in view of the problem that image display devices capable of high resolution and multicolor display are expensive. The present invention aims to inexpensively realize a multi-window type image display device capable of simultaneously displaying , and color display windows.

(Means for Solving the Problems) The apparatus of the present invention which solves the above-mentioned problems comprises a display means capable of color display, and R, G, and H image memory planes, and image data to be displayed on the display means. The stored image memory, the data read out in parallel from this image memory are D/A converted and sent serially to the display means, or the data is divided into blocks of several bits and each block is D/A converted. A programmable D/A converter configured to be able to program whether to perform /A conversion and serially send these to the display means, the programmable D/A converter being programmed in accordance with a read address of the image memory and a control means for correcting the problem.

(Embodiment) FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, 1 is a display means capable of color display, such as a CRT, and 2 is an image memory, R, G.

It consists of B image memory planes 21, 22, and 23, and stores image data to be displayed on the display means 1. 3 is a programmable D provided between the image memory 2 and the display means 1;
The first function is to D/A convert the data read out in parallel from the image memory 2 by the /A converter and send it to the display means l as serial data, and to convert the data read out in parallel from the image memory 2 into several blocks. Divided into
It has a second function that performs D/A conversion for each block and sends it as serial data to the display means l, and a selection function that selects either the first function or the second function. . Reference numeral 4 denotes a mode control memory in which data specifying the operating mode of the programmable D/A converter 3 is stored and read out in synchronization with the image memory 2. 5
is a control circuit that controls the programmable D/A based on the data read from the mode control memory 4.
It controls the operation of the converter 3. 6 is an address generator which connects the image memory 2 via the address bus AB.
and mode control memory 4, and specifies the read address of each memory.

FIG. 2 is a block diagram showing an example of the programmable D/A converter 2. As shown in FIG. This D/A converter includes a parallel data latch circuit 31 that latches parallel data read from the image memory 2, a programmable data selector 32 that selects the latched parallel data according to a control word from the control circuit 5, and a programmable data selector 32 that selects the latched parallel data according to a control word from the control circuit 5. A programmable data mapper 33 that maps the mapped data according to the control word, a D/A converter 34 that inputs the mapped data, and a programmable frequency divider i/D/A that changes the period of the clock CLK given to the D/A converter 34 according to the control word. It is comprised of a programmable reference voltage generator 36 that changes the reference voltage VRef applied to the converter 34 according to a control code.

The operation of the device configured in this manner will be described next. Here, the parallel data output from image memory 2 is 16
Bit.

FIG. 3 is a diagram showing the operation of each memory when addresses are given to the image memory 2 and mode control memory 4 from the address generator 6.

As shown in (a), each of the R, G, and B memory planes of the mode control memory 4 and the image memory 2 are synchronized at the same time and are 16 bits at a time (therefore, a total of 16 bits x 4
= 64 bits) Control words read out from read mode control memory 4 in sequence (read mode)
Since the color representation of one pixel is 8 bits each for R, G, and B, that is, 224 colors (+6.77 million colors), R, G
, B, 1 bit each, that is, 23 colors (8 colors), are dynamically controlled according to the chromaticity in the horizontal scanning direction.

4 to 7 are operational explanatory diagrams showing how the programmable D/A converter 3 is programmed according to the control word from the control circuit 5, in which (a) is a configuration block diagram; (b) is an operation waveform diagram.

FIG. 4 shows the case where the read mode is mode φ,
In the programmable D/A converter as shown in (a), the data selector 32 is R, G.

Select 1 bit (8 colors) of B, and also use Data Mapper 3.
3 is selected data (1 bit) from the data selector 32
are collectively connected to the input end of the D/A converter 34. -Input to D7. The frequency divider 35 is programmed to have a frequency division ratio of x1, and the reference voltage generator 36 is programmed to set the reference voltage VRef to 1. In this programmed state, one pixel consists of one bit each for R, G, and B.

During the cycle time of the image memory 2, 16 dots are displayed as shown in (b), and the resolution in the horizontal scanning direction is maximum in this mode.

FIG. 5 shows the case where the read mode is mode 1,
Data selector 32 has 2 bits each of R, G, and B (64 colors)
, and the data mapper 33 inputs the selected 2-bit data to the input lines Ds and Dy of the D/A converter 34. The division period 35 sets the frequency division ratio to XI/2, and the reference voltage generator 36 sets the reference voltage VRef to 256/1.
Each is programmed to be 92 times larger. In this state, R,G.

One pixel of B is composed of 2 bits each, and the resolution in the horizontal scanning direction is 172 in mode φ.

FIG. 6 shows the case where the read mode is mode 2. Data selector 32 has 4 bits each for R, G, and B (4096 colors)
, and the data mapper 33 inputs the selected 4-bit data to the input terminals D4 to D of the D/A converter 34. The frequency divider 35 sets the frequency division ratio to 174, and the reference voltage generator 36 sets the reference voltage VRef to 256/240.
Each is programmed to double. In this state, one pixel is composed of 4 bits each of R, G, and B, and the resolution in the horizontal scanning direction is 174 in mode φ.

Figure 7 shows the case where the read mode is mode 3. Data selector 32 has R, G, and B bits (16.77 million colors)
, and the data mapper 33 inputs the selected 8-bit data to the input terminals D0 to D7 of the D/A converter 34. The frequency divider 35 is programmed to have a frequency division ratio of 178, and the reference voltage generator 36 is programmed to increase the reference voltage VRef by 1. In this cram school state, R, G
, B each consists of 8 bits, and the number of display colors is 167.
The maximum color is 70,000 colors, but the resolution in the horizontal scanning line direction is 178 in mode φ.

FIGS. 8 and 9 show R, G,B
As shown in (b), each plane stores data specifying the display resolution and number of display colors in accordance with the properties of each screen, in the water pressure corresponding to each window position.

That is, in the position corresponding to the graphic screen, R,
The above-mentioned mode 1 is specified in which one pixel is composed of 2 bits each of G and B (64 colors), and the resolution is 1/2. Also, specify the mode φ mentioned above in the position corresponding to the trend screen, and specify the mode φ in the position corresponding to the real image screen.
Specify the mode 2 mentioned above. Note that the remaining part specifies the mode φ.

By storing the data shown in (b) in the control memory 4, the trend screen can be displayed at maximum resolution, and the real image screen can be displayed with an increased number of displayed colors, although the resolution is slightly lowered. This makes it possible to display images that suit the characteristics of each display screen within one screen.

FIG. 9 is an application example in which an ITV input image is displayed by superimposing within a graphic screen. In the control memory 4, the mode 3 (1 pixel 8 bits
16.77 million colors) resolution 1/8) is specified. By performing such a display, it becomes possible to identify the color of a specific portion (for example, a liquid portion in a beaker).

Note that although the above embodiment assumes that the parallel data output is 16 bits, the number of bits is not limited to this. In addition, the programmable D/A converter 3 also
The configuration is not limited to that shown in FIG. 2. That is, the mode φ of each memory plane xl bit of R, G, and B
If the D/A converter 34 is used in
A D/A converter with a simple configuration can be used. Therefore, for example, only in mode 3 of each plane x 8 bits, an inexpensive 8-bit D/A converter with low speed operation is used, and in other modes, D/A conversion is realized by switching analog switches, etc. With a simple configuration,
An inexpensive programmable D/A converter can be constructed. Furthermore, if the mode control memory 4 is, for example, a multi-window display and the window shape is a regular rectangle,
It is not necessary to have a configuration corresponding to each plane of the image memory 2 and 1=1.

(Effects of the Invention) As explained above, according to the apparatus of the present invention, input images from an ITV color camera can be superimposed on a graphic display screen at high resolution, and multicolor display can be performed only in some windows. Requests such as the case where it is desired to perform the following can be realized using an inexpensive graphic display by means of programmable D/A converter control.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
Figure 1 is a configuration block diagram showing an example of a programmable D/A converter used in the device, Figure 3 is a diagram showing the operation of the image memory and mode control memory, and Figures 4 to 7 are control diagrams. An operation explanatory diagram showing how the programmable D/A converter is programmed according to the control word from the circuit, and FIGS. 8 and 9 are explanatory diagrams showing specific display examples by the apparatus of the present invention. 1... Display means, 2... Image memory, 3... Programmable D/A converter, 4... Mode control memory, 5... Control circuit, 6... Address register. Figure 1

Claims (1)

[Claims] A display means capable of color display; an image memory consisting of R, G, and B image memory planes in which image data to be displayed on the display means is stored; and data read out in parallel from this image memory is D/A converted and serialized. It is configured such that it is possible to program whether to send the data to the display means in serial mode, or to divide several bits into one block, perform D/A conversion for each block, and send the data serially to the display means. An image display device comprising a programmable D/A converter and a control means for reprogramming the programmable D/A converter in accordance with a read address of the image memory.