JPH0827607B2 - Image display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-window type image display device, and more specifically to a high resolution image area and a low resolution but multi-color display. The present invention relates to an image display device capable of displaying areas simultaneously.

(Prior Art) Many conventionally known image display devices (color graphic displays) generally have a fixed display resolution and a simultaneous display color number.

In general, for example, a natural image input by a TV camera does not need to have a high resolution, but requires a large number of display colors. On the other hand, images such as characters and drawings output in CAD do not require a large number of display colors, but high resolution is required.

In an image display device used in a workstation or the like, there are cases where it is desired to display characters, drawings, etc. together with a natural image in a multi-window system. Conventionally, in such a case, an expensive image display device having high resolution and capable of multicolor display has been prepared.

(Problems to be Solved by the Invention) The present invention has been made in view of the problem that an image display device having high resolution and capable of multicolor display becomes expensive, and an object thereof is to provide a high resolution window. And an image display device of a multi-window system capable of simultaneously displaying multi-color display windows.

(Means for Solving Problems) An apparatus of the present invention for solving the above problems comprises a display means capable of color display and multi-window display, and an R, G, B image memory plane. The image memory that stores the image data to be displayed on the display means and the data read in parallel from this image memory are
Programmable switching between A-converted mode and serial data sent to the display means and mode in which several bits are divided into one block and D / A converted for each block and sent to the display means as serial data Programmable D / A converter configured as possible and data designating an operation mode of the programmable D / A converter is stored, and an address corresponding to the read address of the image memory is given to operate in synchronization with the image memory. A mode control memory from which data designating a mode is read, and control means for controlling the operation mode of the programmable D / A converter based on the data read from the mode control memory, High-resolution window and multicolor display window can be displayed simultaneously The image display device is characterized by the above.

(Embodiment) FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, 1 is a display means capable of color display such as a CRT, 2 is an image memory, and an R, G, B image memory plane 2
Image data to be displayed on the display means 1 is stored. Reference numeral 3 denotes a programmable D / A converter provided between the image memory 2 and the display means 1, which performs D / A conversion of data read in parallel from the image memory 2 and sends it to the display means 1 as serial data. The function and the second function of dividing the data read in parallel from the image memory 2 into some blocks, performing D / A conversion for each block, and sending this to the display means 1 as serial data,
It has a selection function of selecting either the first function or the second function. 4 is a mode control memory,
Data for designating the operation mode of the programmable D / A converter 3 is stored here, and is read in synchronization with the image memory 2. A control circuit 5 controls the operation of the programmable D / A converter 3 based on the data read from the mode control memory 4. An address generator 6 is connected to the image memory 2 and the mode control memory 4 via an address bus AB, and specifies a read address of each memory.

FIG. 2 is a configuration block diagram showing an example of the programmable D / A converter 2. This D / A converter includes a parallel data latch circuit 31 that latches parallel data read from the image memory 2, a programmable data selector 32 that selects the latched parallel data according to a control word from the control circuit 5, and the selected data. Programmable data mapper 33 that maps the data according to the control word, D / A converter 34 that inputs the mapped data, clock CLK that is given to D / A converter 34
Reference voltage V given to programmable frequency divider 35 and D / A converter 34
It is composed of a programmable reference voltage generator 36 that changes Ref according to a control code.

The operation of the apparatus thus configured will be described below. Here, the parallel data output from the image memory 2 is 16
Bit.

FIG. 3 is a diagram showing the operation of each memory when an address is given from the address generator 6 to the image memory 2 and the mode control memory 4.

As shown in (a), the mode control memory 4 and each of the R, G, and B memory planes of the image memory 2 are simultaneously synchronized in units of 16 bits (thus 16 bits x 4 = 64 bits in total) in sequence. Read out, horizontal scanning direction (arrow Hy direction)
Go to

(B) is a conceptual diagram of data read simultaneously. The control word (reading mode) read from the mode control memory 4 represents the color expression of one pixel for each of R, G, and B.
Depending on the position in the horizontal scanning direction, the number of bits, that is, 2 ²⁴ colors (16.77 million colors) to 1 bit for each of R, G, and B, that is, 2 ³ colors (8 colors), is dynamically set according to the horizontal scanning position To control.

4 to 7 are operation explanatory diagrams showing how the programmable D / A converter 3 is programmed according to the control word from the control circuit 5, and (a) is a configuration block diagram, (B) is an operation waveform diagram.

FIG. 4 shows the case where the read mode is the mode φ, and in the programmable D / A converter as shown in (a), the data selector 32 has 1 bit of R, G, B (8 colors).
Further, the data mapper 33 collects the selected data (1 bit) from the data selector 32 and inputs it to the input terminals D _{0 to} D ₇ of the D / A converter 34. The frequency divider 35 has a division ratio of × 1.
The reference voltage generator 36, the reference voltage VRef
Are each programmed to be 1 time. When programmed in this way, R, G, and B are 1 bit each.
Pixels are constructed. During the cycle time of the image memory 2, 16 dots are displayed as shown in (b), and the resolution in the horizontal scanning direction is maximized in this mode.

FIG. 5 shows the case where the read mode is mode 1, the data selector 32 selects R, G, and B each 2 bits (64 colors), and the data mapper 33 outputs the selected 2-bit data to D /
Input to the input terminals D ₆ and D ₇ of the A converter 34. The frequency divider 35 is
The division ratio is set to × 1/2, and the reference voltage generator 36 is programmed so that the reference voltage VRef becomes 256/192 times. In this state, R, G, and part are 2 bits each and 1
Pixels are formed, and the resolution in the horizontal scanning direction is half that in the mode φ.

FIG. 6 shows the case where the read mode is mode 2. The data selector 32 selects each of R, G, B 4 bits (4096 colors), and the data mapper 33 selects the selected 4 bit data by D / A.
Input to the input terminals D _{4 to} D ₇ of the converter 34. The frequency divider 35 is programmed to have a frequency division ratio of 1/4, and the reference voltage generator 36 is programmed to have a reference voltage VRef of 256/240 times. In this state, one pixel is composed of 4 bits for each of R, G, and B, and the horizontal scanning direction resolution is 1/4 that of the mode φ.

FIG. 7 shows the case where the read mode is mode 3. The data selector 32 selects R, G, and B bits (16.77 million colors), and the data mapper 33 selects the selected 8-bit data from D / A.
Input to the input terminals D _{0 to} D ₇ of the converter 34. The frequency divider 35 is programmed to have a frequency division ratio of 1/8, and the reference voltage generator 36 is programmed to have a reference voltage VRef of 1. In this state, one pixel is composed of 8 bits for each of R, G, and B, and the number of display colors is maximum at 16.77 million colors, but the resolution in the horizontal scanning direction is 1/8 of that in the mode φ.

8 and 9 are explanatory views showing specific display examples by the device of the present invention.

As shown in FIG. 8 (a), when it is attempted to display three kinds of screens of a graphic screen, a trend screen and a real image from the ITV camera on the display means 1 in a multi-window display, In each plane of R, G, B, as shown in (b), at a position corresponding to each window position, according to the nature of each screen,
Stores data that specifies the display resolution and the number of display colors.

That is, at the position corresponding to the graphic screen, R,
Designate the above-mentioned mode 1 such that one pixel is composed of 2 bits for each of G and B (64 colors) and the resolution is 1/2. Further, the above-mentioned mode φ is designated at the position corresponding to the trend screen, and the above-mentioned mode 2 is designated at the position corresponding to the real image screen. The remaining part is designated as mode φ.

By storing the data having the contents shown in (b) in the control memory 4, the trend screen is displayed at the maximum resolution, and the real image screen is slightly lowered in resolution but the number of display colors is increased. It is possible to display, and it is possible to display within one screen a display suitable for the property of each display screen.

FIG. 9 is an application example in which an ITV input image is displayed by superimposing on a graphic screen. In the control memory 4, the above-mentioned mode 3 (1 pixel 8 bits × 3 (16.77 million colors) resolution 1/8) is designated at a position corresponding to the inside of the bold line. By performing such a display, it is possible to identify the color of a specific portion (for example, the liquid portion in the beaker).

In the above embodiment, the case where the parallel data output is 16 bits can be assumed, but the number of bits is not limited. Also, the programmable D / A converter 3 is not limited to the configuration shown in FIG. That is, if the R, G, and B memory planes are used in the mode φ of 1 bit, the D / A converter 34 is not necessary, and if each memory plane is 4 bits or less, it is simple. A configuration D / A converter can be used. Therefore, for example, only in the case of mode 3 of each plane × 8 bits, an inexpensive 8-bit D / A converter operating at low speed is used, and in other modes, D / A conversion is realized by switching an analog switch or the like. By doing so, an inexpensive programmable D / A converter can be configured with a simple configuration. Further, the mode control memory 4 does not have to have a configuration corresponding to each plane of the image memory 2 in a 1: 1 manner, for example, in the case of multi-window display and the window having a rectangular fixed shape.

(Effects of the Invention) As described above, according to the device of the present invention, an input image from an ITV color camera can be superimposed at a high resolution on a graphic display screen, or only some windows can be displayed in multiple colors. It is possible to meet the demands such as the case of using an inexpensive graphic display by the programmable D / A converter control method.

Further, according to the device of the present invention, a high-resolution window and a multicolor display window can be simultaneously displayed on the screen of the display means, and a screen in which fine line information and surface information expressed in multicolor are mixed is displayed. It can be displayed as if it were a high-grade graphic display device.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, and FIG.
The figure shows the programmable used in the device in Figure 1.
FIG. 3 is a configuration block diagram showing an example of a D / A converter, FIG. 3 is a diagram showing operations of an image memory and a mode control memory,
4 to 7 are operation explanatory diagrams showing how the programmable D / A converter is programmed according to the control word from the control circuit, FIG. 8 and FIG.
The figure is an explanatory view showing a specific display example by the device of the present invention. 1 ... Display means, 2 ... Image memory, 3 ... Programmable D /
A converter, 4 ... Mode control memory, 5 ... Control circuit, 6 ... Address register.

Claims (1)

[Claims] 1. A display means capable of color display and multi-window display; an image memory comprising R, G, B image memory planes for storing image data to be displayed on said display means; Data read in parallel from the D / A
It is possible to programmably switch between the mode in which the data is converted and sent out as serial data to the display means and the mode in which some bits are divided into one block and D / A converted for each block and sent out as serial data in the display means. A programmable D / A converter configured as described above, and data designating an operation mode of the programmable D / A converter is stored, an address corresponding to the read address of the image memory is given, and the operation mode is synchronized with the image memory. A mode control memory from which data designating is read, and control means for controlling the operation mode of the programmable D / A converter based on the data read from the mode control memory, and within the screen of the display means. High-resolution window and multicolor display window can be displayed simultaneously An image display device comprising that there was Unishi.