JPS63106131U - - Google Patents
Info
- Publication number
- JPS63106131U JPS63106131U JP20008386U JP20008386U JPS63106131U JP S63106131 U JPS63106131 U JP S63106131U JP 20008386 U JP20008386 U JP 20008386U JP 20008386 U JP20008386 U JP 20008386U JP S63106131 U JPS63106131 U JP S63106131U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- element attachment
- stamp
- solder paste
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図は、本考案に係る半導体装置の半田ペー
スト塗着方法を説明するための断面図、第２図は
、本考案に係る半導体装置の要部のみの断面図で
ある。 １…素子取付用基板、２…半田ペースト、３…
素子、４…突起部、５…スタンプ。
スト塗着方法を説明するための断面図、第２図は
、本考案に係る半導体装置の要部のみの断面図で
ある。 １…素子取付用基板、２…半田ペースト、３…
素子、４…突起部、５…スタンプ。
Claims (1)
- 素子取付用基板に、素子を、スタンプ先端で塗
着した半田ペーストを加熱溶融して取付けるよう
にした半導体装置において、前記素子取付用基板
の素子取付位置近傍に、スタンプ先端の半田ペー
ストを掻き落とす突起部を設けたことを特徴とす
る半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20008386U JPS63106131U (ja) | 1986-12-26 | 1986-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20008386U JPS63106131U (ja) | 1986-12-26 | 1986-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63106131U true JPS63106131U (ja) | 1988-07-08 |
Family
ID=31162266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20008386U Pending JPS63106131U (ja) | 1986-12-26 | 1986-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63106131U (ja) |
-
1986
- 1986-12-26 JP JP20008386U patent/JPS63106131U/ja active Pending