JPS63105998U - - Google Patents
Info
- Publication number
- JPS63105998U JPS63105998U JP20242386U JP20242386U JPS63105998U JP S63105998 U JPS63105998 U JP S63105998U JP 20242386 U JP20242386 U JP 20242386U JP 20242386 U JP20242386 U JP 20242386U JP S63105998 U JPS63105998 U JP S63105998U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- parallel
- capacitors
- power supply
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Static Random-Access Memory (AREA)
- Stand-By Power Supply Arrangements (AREA)
- Power Sources (AREA)
Description
第１図は、本考案のメモリバツク・アツプ回路
の一実施例の回路図であり、第２図は、電源から
直流電圧がメモリに印加されているときのコンデ
ンサの接続を示す図であり、第３図は、電源が遮
断されているときのコンデンサの接続を示す図で
あり、第４図は、第１図の構造によりバツク・ア
ツプ時間を長くすることができる説明図であり、
第５図は、従来のメモリバツク・アツプ回路の一
例の回路図である。
２：電源回路、４：メモリ、６，８：コンデン
サ、７：スイツチ。
FIG. 1 is a circuit diagram of one embodiment of the memory backup circuit of the present invention, and FIG. 2 is a diagram showing the connection of capacitors when DC voltage is applied to the memory from the power supply. FIG. 3 is a diagram showing the connection of the capacitor when the power supply is cut off, and FIG. 4 is an explanatory diagram showing how the structure of FIG. 1 can lengthen the back-up time.
FIG. 5 is a circuit diagram of an example of a conventional memory backup circuit. 2: Power supply circuit, 4: Memory, 6, 8: Capacitor, 7: Switch.
Claims (1)
ときに、複数のコンデンサの直列接続体が前記メ
モリに並列接続され、前記電源が遮断されている
ときに、前記複数のコンデンサが互いに並列接続
され、このコンデンサの並列接続体が前記メモリ
に並列接続されることを特徴とするメモリバツク
・アツプ回路。 When a DC voltage is applied to the memory from a power supply, a series connection body of a plurality of capacitors is connected in parallel to the memory, and when the power supply is cut off, the plurality of capacitors are connected in parallel to each other, A memory back-up circuit characterized in that this parallel connection of capacitors is connected in parallel to the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20242386U JPH035040Y2 (en) | 1986-12-26 | 1986-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20242386U JPH035040Y2 (en) | 1986-12-26 | 1986-12-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63105998U true JPS63105998U (en) | 1988-07-08 |
| JPH035040Y2 JPH035040Y2 (en) | 1991-02-08 |
Family
ID=31166791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20242386U Expired JPH035040Y2 (en) | 1986-12-26 | 1986-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH035040Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02121531A (en) * | 1988-10-31 | 1990-05-09 | Nec Corp | Portable radio telephone system |
| JP2019205287A (en) * | 2018-05-24 | 2019-11-28 | 三菱電機株式会社 | Power conversion apparatus and dc power supply system |
-
1986
- 1986-12-26 JP JP20242386U patent/JPH035040Y2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02121531A (en) * | 1988-10-31 | 1990-05-09 | Nec Corp | Portable radio telephone system |
| JP2019205287A (en) * | 2018-05-24 | 2019-11-28 | 三菱電機株式会社 | Power conversion apparatus and dc power supply system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH035040Y2 (en) | 1991-02-08 |