JPS63104474A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63104474A JPS63104474A JP25233286A JP25233286A JPS63104474A JP S63104474 A JPS63104474 A JP S63104474A JP 25233286 A JP25233286 A JP 25233286A JP 25233286 A JP25233286 A JP 25233286A JP S63104474 A JPS63104474 A JP S63104474A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- base
- polycrystalline silicon
- metal dust
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000000992 sputter etching Methods 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000001312 dry etching Methods 0.000 claims description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000460 chlorine Substances 0.000 abstract description 3
- 229910052801 chlorine Inorganic materials 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- 239000000428 dust Substances 0.000 abstract 4
- 239000002253 acid Substances 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は加速されたイオンにL9半導体装t’に製造す
る方法に関する1、
〔従来の技術〕
半導体装置の製造工程はウェットプロセスからドライプ
ロセスと移、ってきているがその中の電極形成工程もイ
オンミリング法が主流になってきた。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing L9 semiconductor devices t' using accelerated ions. [Prior Art] The manufacturing process of semiconductor devices varies from wet process to dry process. However, the ion milling method has become mainstream in the electrode formation process.
特に超高周波トランジスタの様にエミッタ・ペース間距
離が数μm程度という構造に対してはウェットプロセス
はサイドエッチ量のコントロールが非常に難しく不安定
であった。一方、イオンミリング法はサイドエッチ量の
全んど無い条件が得られるのでマスクパターン通9の寸
法仕上りを得ることが出来る様になった。In particular, for structures such as ultra-high frequency transistors in which the emitter-to-pace distance is on the order of several micrometers, the wet process is unstable because it is extremely difficult to control the amount of side etching. On the other hand, since the ion milling method provides conditions with no side etching, it has become possible to obtain the dimensional finish of the mask pattern 9.
上述した従来のイオンミリング法は第2図の如く数℃の
高電圧で加速されたアルゴンイオンが半導体基板主面に
垂直に当るためエツチングされた金属屑が約45°方向
に飛散し段差部側壁に再付着してE、B間が電気的にシ
ョートされるといり欠点がある。In the conventional ion milling method described above, as shown in Figure 2, argon ions accelerated at a high voltage of several degrees Celsius hit the main surface of the semiconductor substrate perpendicularly, so etched metal scraps are scattered in a direction of approximately 45 degrees, causing the sidewalls of the stepped portions to be damaged. This has the disadvantage that it re-attaches to the surface and causes an electrical short between E and B.
本発明のイオンミリング法はエミッタ・ベース電極をマ
スクにして塩素系ガスに工9多結晶シリコンをエツチン
グし、さらにイオンミリングを行い再付着した金属屑全
除去することを特徴とじている。The ion milling method of the present invention is characterized by etching polycrystalline silicon using a chlorine-based gas using the emitter/base electrode as a mask, and then performing ion milling to remove all redeposited metal debris.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(C)は本発明の一実施例の縦断面図で
ある。1は半導体基板、2はベース領域、3はエミッタ
領域、4は絶縁物、5は多結晶シリコン、6はエミッタ
電極、7はベース電極、8は再付着金属である。従来、
イオンミリングを行うと、約45゜方向に被エツチング
材が飛散してしまう。(図(a))が、この後エミッタ
・ベース電極をマスクにして多結晶シリコン全塩素系ガ
スにてドライエツチングを行う。(図(b))このとき
、酸系のウェットエッチではサイドエッチ量がコントロ
ールが出来ないので、超高周波トランジスタのような目
合せマージンの少ないものは適用出来ない。次に、再度
イオン・ミリング行い金属屑8を除去する。(図(C)
)〔発明の効果〕
以上説明したように本発明は多結晶シリコンをエツチン
グすることにエフエミッタ・ペース電極間が広くなり、
再度長材層してもショートしないという効果がある。FIGS. 1(a) to 1(C) are longitudinal sectional views of an embodiment of the present invention. 1 is a semiconductor substrate, 2 is a base region, 3 is an emitter region, 4 is an insulator, 5 is polycrystalline silicon, 6 is an emitter electrode, 7 is a base electrode, and 8 is a redeposited metal. Conventionally,
When ion milling is performed, the material to be etched is scattered in a direction of about 45 degrees. (FIG. (a)) shows that dry etching is then performed using a polycrystalline silicon all-chlorine gas using the emitter and base electrodes as masks. (Figure (b)) At this time, since the amount of side etching cannot be controlled with acid-based wet etching, it cannot be applied to devices with small alignment margins such as ultra-high frequency transistors. Next, ion milling is performed again to remove metal debris 8. (Figure (C)
) [Effects of the Invention] As explained above, the present invention is effective in etching polycrystalline silicon by widening the distance between the emitter and the paste electrode.
There is an effect that short-circuits will not occur even if the long material layer is applied again.
第1図(a)〜(C)は本発明の製造工程を示す縦断面
図、第2図は従来のイオンミリングを行っているところ
の縦断面図である。FIGS. 1A to 1C are vertical cross-sectional views showing the manufacturing process of the present invention, and FIG. 2 is a vertical cross-sectional view showing conventional ion milling.
Claims (1)
を用いる半導体装置の製造方法において、イオンミリン
グを行う工程とエミッタ・ベース電極をマスクにして多
結晶シリコンを塩素系ガスによりドライエッチを行った
後、イオンミリングを行うことを特徴とする半導体装置
の製造方法。In a semiconductor device manufacturing method that uses ion milling to form electrodes on a semiconductor substrate, the ion milling process and the dry etching of polycrystalline silicon with chlorine gas using the emitter and base electrodes as masks are performed. A method for manufacturing a semiconductor device, characterized by performing ion milling.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25233286A JPH0616511B2 (en) | 1986-10-22 | 1986-10-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25233286A JPH0616511B2 (en) | 1986-10-22 | 1986-10-22 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63104474A true JPS63104474A (en) | 1988-05-09 |
JPH0616511B2 JPH0616511B2 (en) | 1994-03-02 |
Family
ID=17235794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25233286A Expired - Lifetime JPH0616511B2 (en) | 1986-10-22 | 1986-10-22 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0616511B2 (en) |
-
1986
- 1986-10-22 JP JP25233286A patent/JPH0616511B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0616511B2 (en) | 1994-03-02 |
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