JPS63104443A - Large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To operate an LSI chip at low power consumption in such a way that a clock frequency and a power source voltage to be supplied to each function block can be changed. CONSTITUTION:Two or more function blocks inside an LSI chip must be operated at high speed, can be operated sufficiently at low speed, are brought to a standstill, are kept operating, etc. The power consumption differs at each function block according to the operating state. For this, a frequency-dividing circuit of a clock and a voltage-dividing circuit of a power source are installed inside the LSI chip so that their output can be selected on the basis of the information which is arranged in a programmable register. If the operating state of the LSI chip is changed, the clock frequency and the power source voltage which are to be supplied to each function block can be selected according to the requirement. Through this constitution, it is possible to control the power consumption in a dynamic manner in order to operate the LSI chip at low power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to large-scale integrated circuits such as microprocessors and logic LSIs, and particularly to a circuit configuration method suitable for reducing power consumption.

[Conventional technology]

In conventional LSIs, for example, as introduced in the Hitachi Microcomputer Data Book 8-bit single chip, the LSI input terminal (STBY)
goes into standby mode, stops all internal clocks, and goes into ryat state. This causes the LSI to stop operating and only the internal memory retains data.
This aims to reduce power consumption.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the entire -1LSI chip is stopped and enters a low power consumption mode, but in the normal operation mode, all the internal parts of the LSI are operating.

But 1. As the scale of the SI becomes larger and various functions are installed, power consumption increases when the entire LSI is operated, which poses a problem in design. On the other hand, if control is performed only by the 5TAND BY input terminal as in the prior art described above, the entire LSI will stop, making it impossible to operate large-scale Ts and SIs in a low power consumption state.

The present invention aims to achieve low power consumption while allowing the LSI to operate normally.

[Means for solving problems]

Recent LSIs are often constructed in the form of building blocks, with functional blocks called macrocells, megacells, or modules as units. r like this,
, SI, the above purpose is to separate the clock and power supply lines supplied to each functional block, and to create a programmable function that allows the clock frequency and power supply voltage supplied to each functional block to be made variable. This is achieved by on-chip the top.

[Effect]

There are various functional blocks inside an LSI, such as some that require high-speed operation, some that require low-speed operation, some that stop for a certain period of time, and some that only need to maintain their operating state. The following conditions are possible. The power consumption of each functional block differs depending on each state. In the present invention, in order to flexibly control the above-mentioned operating states of each functional block inside the LSI,
A clock frequency dividing circuit and a power supply voltage dividing circuit are provided inside the SI, and the output thereof can be selected based on information set in a programmable register.

(2) When the operating state of the SI chip changes, the clock frequency and power supply voltage supplied to each functional block can be selected as necessary. As a result, power consumption can be dynamically controlled and a large-scale LSI with low power consumption becomes possible.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 is an example of a large-scale LSI in which a programmable clock supply circuit and a programmable power supply voltage supply circuit according to the present invention are integrated on a chip. FIG. 2 shows 1. when realized by the conventional method. This is an example of the configuration of SI. First, second
The configuration and operation of the LSI will be explained with reference to the figure.

LSI has multiple functional blocks, such as CPU, R
OM, RAM, Ilo, C0NTR0LLOR.

MMU (Memory Management)
Unit) DMAC (Direct Meio
ry AccfIss Controller), C
omniCation Processor, D
ispl, oy cont, rollor etc.
Dress Bus, Data Flus, multiple control signal lines (Control Signal Tine)
s).

In the conventional method, a clock manually input from an input terminal passes through a clock circuit, and a signal of the same frequency is supplied to each functional block inside the chip.

Power was also supplied directly from the input terminal. Therefore, depending on the operating state 1 of each functional block,
It was impossible to control clock frequency and power supply voltage.

For example, the fastest CPU goes to the MMU,
When a memory (ROM) address is output via the Address Bus, MMT, J converts the address value, outputs this result to the Address Bus, and the instruction data at a certain address in the ROM is read out using that value. Ru. The instruction data is transferred to C via the Data Bus.
The data is imported into the PU and then stored in RAM, for example.
Similarly to the above, reading is performed through address conversion of M and MU, or the operation result is written to RAM. While data is being exchanged between the CPU, ROM, RAM, and MMU functional blocks,
M.A.C.,CommunicationProce
ssor, Display Controller
, I/0Contro11. If or has never been activated, these functional blocks may be in a stopped state, the clock supply may be stopped, and the power supply voltage may be lowered. As a result, in T and Sr that use CMO 8 times MU: t-
There is no through current in the transistor, and no power is consumed during operation. There is also memory within each functional block.

When there is an information storage circuit such as a register, power consumption for information retention can be reduced by lowering the power supply voltage. Next is the CPU, ROM, and so on.

If you want to perform data communication with the outside of the LSI when only the RAM and MMU are running, use the Communic
tion Processor must be started. At this time, the CPU runs Progra shown in FIG.
mmable C1ock 5uply C1rcu
j, t and Programmable Power 5u
pply C1reuj, t Communicati
Transfer the data to start the on Processor, and set the clock supply and power supply voltage to the operating voltage.

As a result, multiple clock supply lines (C1ockSupp
ly Lines) and power supply lines (Power 5up
plyLj, nes), Communicati
A clock signal of an operating frequency and an operating voltage are supplied to each one coupled to the on Processor.

Combined Communication fed by them
The Processor is started and then, for example, c
The address from pu is sent via Address Bus, Con+n+unication Process
sor is selected. After that, the CPU
Commands and transfer data for operating the cation Processor are sent via the Data Bus. As a result, Communication Pro
A cessor independently transfers data to the outside according to its own sequence of operations. At this time, if the external data transfer speed is slow, Communication Pr
If the operating speed of the ocessor can be lowered, the clock frequency to be supplied can be increased.
j, cationProcessor block can be reduced in power consumption.

After the Communication Processor has finished operating, the Display Control
When outputting the contents of the RAM to an external display device using the CPU, the CPU again sends the clock frequency data and voltage selection data to each functional block to the programmable clock supply circuit and programmable power supply circuit. It will be done. Con+monicatjon Proc
When the essor does not need to operate, the clock supply to it is stopped and the power supply voltage is lowered. Also RAM and Di
The data transfer between playControl, ], or is under the control of DMAC without involving the operation of the CPU.
Direct RAM and Display Controller
It can be done between.

This method is often used for high-speed data transfer between memory and input/output devices. In this case, since address translation by the MMU is not required, the operation of the MMTJ may be stopped. Therefore, while stopping the clock supply to the MMU and switching to the power supply voltage at the time of stop, Displ
A clock is supplied to the ay Controller and an operating power supply voltage is supplied. In this way, after clocks and operating voltages are supplied to the functional blocks necessary for operation, the CPU
lor, sends DMAC commands and data, and starts each. Here again, RAM and Display
For data transfer to and from the Controller, C
If a faster clock than PU is required, DMA
The clock supply line (C1ock Hnes) to C, Display Control, or
A higher frequency clock will be supplied. As a result, these functional blocks consume more power than other parts during this operating state.

However, since the power consumption in other blocks can be reduced, it is possible to prevent the power consumption of the entire LSI from increasing.

This enables clock supply control and power supply voltage supply control as described above. Programmable clock supply circuit (Prog
rammable clock 5upply C1r
Figure 3 shows the programmable power supply voltage supply circuit (Programmable Power 5upp).
lyC1rcuit) is shown in FIG.

As shown in FIG. 3, a frequency dividing circuit and a plurality of functional blocks A divide the frequency like a programmable clock.

Programmable registers (registers A, B.

C, D) and selectors A, B, C that select multiple outputs of the frequency divider by programmable registers.

D, Drit, a Bus value programmable register A.

Register selection Ad when transferring to B, C, D
The decoder and clock of the dress Bus value are set to L.
It consists of multiple driver circuits for supplying to the SI chip.

For example, register A has L S B (L
M from eastSignificant Bit)
SB (Most Sognjificant Bi
When the value "o o o o" is set to t), all the outputs of the frequency divider circuit are not selected and no clock is supplied to the internal clock line A.

When “1000” is set in Register B, one output of the frequency divider circuit is selected and the internal clock m
B is supplied with a clock having a frequency of -.f. Similarly, “00” is entered in Registers C and D in FIG.
When "10" and "0001" are set, clocks having frequencies of -f and f are supplied to internal clock lines C and D, respectively.

As shown in Figure 4, the programmable power supply voltage circuit (Pr
ogrammable Power 5upply C
1rcuit) connects the input voltage from the Power 5upply terminal to a voltage divider circuit and multiple internal power lines E and F.
, and programmable registers Register E and F that specify the voltage to be supplied to GH.

In order to set the G, H and Data BusO values to the above registers, the outputs of the ADDRESS Bus decoder circuit and voltage divider circuit are sent to Registers E and F.
, G, H select switch Ex, E2
, F Eng, Fx, Gz, Gz.

Consists of H1 and H2. As shown in Figure 4, Re
gister E's LSB is 111", MSB is it
When Otp is set, the internal power supply line E is supplied with the value of 3cm of the output of the voltage dividing circuit. Register F,
Since 1101-I+ is set for G and H, the 5V value of the output of the voltage divider circuit is connected to the internal power supply lines F, G, and H.
supplied to

Among Regjster E, F, G, H, the register selected by ADDRESS Bus is Da.
The value of ta Bus is set at the timing of Control153gna'J-, and the data for selecting the output value of the 1 voltage divider circuit can be changed.

〔Effect of the invention〕

According to the present invention, in a high-performance LSI chip equipped with hundreds of thousands to millions of transistor elements, it is possible to reduce the power consumption, which is more than several att in the conventional method and is likely to increase further in the future. microcomputers and logic LSIs equipped with several million transistors.
It is effective for practical application.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a large-scale integrated circuit having a programmable clock supply circuit and a power supply circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a programmable clock supply circuit and a power supply circuit according to an embodiment of the present invention.
FIG. 3 is a block diagram of a conventional large-scale integrated circuit without a power supply circuit, FIG. 3 is a block diagram of a programmable clock supply circuit, and FIG. 4 is a block diagram of a programmable power supply circuit.

Claims (1)

[Claims] A plurality of functional blocks connected by one or more address buses, data buses, and control signal lines, and which are similarly connected and divide an input clock by a plurality of frequency division ratios. A clock with a frequency obtained by the circuit to be rotated and each frequency division ratio can be selected for each of the above functional blocks and supplied via the clock supply line to each, so that the frequency can be selected arbitrarily. A large-scale integrated circuit with an on-chip programmable clock supply circuit made up of programmable registers. 2. A plurality of functional blocks connected by one or more address buses, data buses, and control lines, and a circuit that is similarly connected and divides the input power supply voltage into a plurality of voltage values; The voltage obtained by the voltage ratio can be selected for each of the above functional blocks and supplied through the power supply voltage supply line to each, and the voltage value can be arbitrarily selected using programmable registers. 2. The large-scale integrated circuit according to item 1, which includes a programmable power supply circuit on-chip.