JPS63104424A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS63104424A JPS63104424A JP24965186A JP24965186A JPS63104424A JP S63104424 A JPS63104424 A JP S63104424A JP 24965186 A JP24965186 A JP 24965186A JP 24965186 A JP24965186 A JP 24965186A JP S63104424 A JPS63104424 A JP S63104424A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electron beam
- vacuum
- inorganic film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000010894 electron beam technology Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 12
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000000126 substance Substances 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- -1 hydrocarbon Chemical compound 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置の!!12造方法に関し
、特に、フォトリソグラフィーでは実現国電な微細なパ
ターンを形成するのに適用して有効な技術に関するもの
である。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to semiconductor integrated circuit devices! ! This article relates to 12 manufacturing methods, and in particular, to photolithography, which is an effective technique that can be applied to form fine patterns that can be realized.
近時、半導体集積回路装置においては、素子の微細化に
伴い、サブミクロン幅の微細パターンを形成する技術が
極めて重要となっている。2. Description of the Related Art Recently, in semiconductor integrated circuit devices, with the miniaturization of elements, techniques for forming fine patterns with submicron widths have become extremely important.
しかしながら、光を用いた従来の露光方式では幅が0.
5μm程度以下の微細なパターンを形成することは不可
能である。一方、この光露光方式に代わる技術として、
より短波長の電子ビームを用いた露光方式があるが、こ
の場合には入射電子の後方散乱の効果等により電子線レ
ジストの解像度が電子線の波長から期待されるよりも低
くなる。However, in the conventional exposure method using light, the width is 0.
It is impossible to form a fine pattern of about 5 μm or less. On the other hand, as an alternative technology to this light exposure method,
There is an exposure method using an electron beam with a shorter wavelength, but in this case, the resolution of the electron beam resist becomes lower than expected from the wavelength of the electron beam due to the effect of backscattering of incident electrons.
すなわち、電子線レジス1〜により微細化が制約されて
しまうという問題がある。That is, there is a problem that miniaturization is restricted by the electron beam resists 1 to 1.
本発明の目的は、電子ビームの径と同程度の幅の極めて
微細なパターンを容易に形成することが可能な技術を提
供することにある。An object of the present invention is to provide a technique that can easily form an extremely fine pattern with a width comparable to the diameter of an electron beam.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本発明者は、上述のような従来技術の欠点を是正すべく
鋭意検討した結果、比較的真空度の悪い真空中で任意の
面に電子ビームを照射すると、真空中に含まれる残留ガ
ス中の有機物質がこの電子ビームにより分解して前記面
に堆積する結果、この照射領域に少なくとも炭素を含む
微細な物質層が形成されることを見出し、これに基づい
て本発明を案出するに至った。As a result of intensive studies to correct the drawbacks of the prior art as described above, the inventor of the present invention discovered that when an arbitrary surface is irradiated with an electron beam in a vacuum with a relatively poor degree of vacuum, the residual gas contained in the vacuum is The inventors have discovered that as a result of organic substances being decomposed by the electron beam and deposited on the surface, a fine material layer containing at least carbon is formed in the irradiated area, and based on this finding, the present invention has been devised. .
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。Outline of typical inventions disclosed in this application is as follows.
すなわち、比較的真空度の低い真空中で電子ビームを照
射することにより形成される少なくとも炭素を含む物質
層をエツチングマスクとして用いるようにしている。That is, a material layer containing at least carbon, which is formed by irradiating an electron beam in a relatively low degree of vacuum, is used as an etching mask.
上記した手段によれば、電子ビームの径と同程度の幅の
微細な物質層から成るエツチングマスクを形成すること
ができるので、このエツチングマスクを用いて被エツチ
ング膜をエツチングすることにより、この電子ビームの
径と同程度の幅の極めて微細なパターンを容易に形成す
ることができる。According to the above-mentioned means, it is possible to form an etching mask made of a fine material layer with a width comparable to the diameter of the electron beam. An extremely fine pattern with a width comparable to the diameter of the beam can be easily formed.
以下、本発明の箭成について、一実施例に基づき図面を
参照しながら説明する。The arrangement of the present invention will be described below based on one embodiment with reference to the drawings.
なお、全図において、同一・の機能を有するものには同
一の符号を伺け、その繰り返しの説明は省略する。In all figures, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.
第1図に示すように、まず例えばP型シリコン基板のよ
うな半導体基板1の表面を選択的に熱酸化することによ
り5i02膜がら成るフィールド絶縁膜2を形成して素
子分離を行った後、このフィールド絶縁膜2で囲まれた
活性領域表面に例えばSiO2膜のようなグー1〜絶縁
膜3を形成し、さらにこのゲート絶縁膜3上に例えば多
結晶シリコン=3−
膜から成るゲート電極4を形成する。次に、このゲート
電極4をマスクとしてn型不純物を半導体基板l中にイ
オン打ち込みすることにより例えばII”型のソース領
域5及びドレイン領域6を前記ゲート電Fi4に対して
セルファラインに形成する。As shown in FIG. 1, first, by selectively thermally oxidizing the surface of a semiconductor substrate 1 such as a P-type silicon substrate, a field insulating film 2 made of a 5i02 film is formed to perform element isolation. On the surface of the active region surrounded by this field insulating film 2, insulating films 1 to 3, such as SiO2 films, are formed, and further on this gate insulating film 3, a gate electrode 4 made of, for example, a polycrystalline silicon film is formed. form. Next, using this gate electrode 4 as a mask, n-type impurities are ion-implanted into the semiconductor substrate l, thereby forming, for example, a II'' type source region 5 and drain region 6 in a self-alignment line with respect to the gate electrode Fi4.
次に、全面に例えばリンシリケートガラス(PSG)膜
や5102膜のような層間絶縁膜7を形成した後、この
層間絶縁膜7の所定部分をエツチング除去してコンタク
トホール7a、7bを形成する。Next, after forming an interlayer insulating film 7 such as a phosphosilicate glass (PSG) film or a 5102 film on the entire surface, predetermined portions of the interlayer insulating film 7 are removed by etching to form contact holes 7a and 7b.
次に、例えばスパッタ法により全面に例えばアルミニウ
ム膜8を形成した後、このアルミニウム膜8上に平坦化
用の有機膜9を塗布する。この塗布後の有機膜9の表面
は平坦になる。次に、この有機膜9上に膜厚が例えば0
.1μm程度の薄いスピンオンガラス(SOG)膜のよ
うな無機膜lOを塗布する。なお、これらの無機膜10
及び有機膜9は必ずしも必要ではなく、必要に応じて省
略可能である。Next, for example, an aluminum film 8 is formed on the entire surface by, for example, sputtering, and then an organic film 9 for planarization is applied on this aluminum film 8. The surface of the organic film 9 after this coating becomes flat. Next, a film thickness of, for example, 0 is applied on this organic film 9.
.. An inorganic film lO such as a spin-on glass (SOG) film with a thickness of about 1 μm is applied. Note that these inorganic films 10
The organic film 9 is not necessarily required and can be omitted if necessary.
次に、前記半導体基板1を電子ビーム描画装置の真空室
に入れ、その真空度が比較的低い状態番ミおいてビーム
径を例えば0.5〜0.01μm0程度に絞った電子ビ
ー1z 11を走査することにより、後述の配線12に
対応する位置における前記無機膜10の表面を電子ビー
ム11で照射する。これにより、真空中の残留ガス中に
含まれる例えば炭化水素のような有機物質がこの電子ビ
ーム11の照射により分解して前記無機膜10上に堆積
する結果、第2図に示すように、この電子ビーム11で
照射された部分における前記無機膜lOの表面に少なく
とも炭素を含む物質層12が形成される。Next, the semiconductor substrate 1 is placed in a vacuum chamber of an electron beam lithography apparatus, and the electron beam 1z 11 is placed in a relatively low vacuum state and the beam diameter is narrowed to, for example, about 0.5 to 0.01 μm. By scanning, the surface of the inorganic film 10 at a position corresponding to a wiring 12 to be described later is irradiated with the electron beam 11. As a result, organic substances such as hydrocarbons contained in the residual gas in the vacuum are decomposed by the irradiation of the electron beam 11 and deposited on the inorganic film 10, as shown in FIG. A material layer 12 containing at least carbon is formed on the surface of the inorganic film IO in the portion irradiated with the electron beam 11.
この物質層12の幅は、前記電子ビーム11の径と同程
度であり、極めて小さい。なお、前記真空室内に例えば
炭化水素のような少なくとも炭素を含むガスを導入し、
この状態で電子ビーム11の照射を行ってもよい。The width of this material layer 12 is approximately the same as the diameter of the electron beam 11, which is extremely small. Note that introducing a gas containing at least carbon, such as hydrocarbon, into the vacuum chamber,
Irradiation with the electron beam 11 may be performed in this state.
次に第3図に示すように、この物質層12をマスクとし
て前記無機膜10を例えばドライエツチングすることに
より無機膜から成る所定パターンを形成する。この場合
、前記無機膜lOは極めて薄く、かつドライエツチング
の際の物質層12との選択比が大きいので、物質層12
の厚さが小さくても無機膜10をパターンニングするこ
とが可能である。次に、この所定パターンをマスクとし
て例えば反応性イオンエツチング(R,IE)により前
記有機膜9を基板表面と垂直方向に異方性エツチングす
ることにより、有機膜から成る所定パターンを形成した
後、この所定パターンをマスクとして前記アルミニウム
膜8を例えばRIEにより異方性エツチングすることに
より配線パターン13を形成する。このようにして形成
される配線パターン13のうち幅の小さい配線部分は、
前記電子ビーム11の径と同程度の幅を有し、従って極
めて微細な配線13を形成することができる。Next, as shown in FIG. 3, using this material layer 12 as a mask, the inorganic film 10 is subjected to, for example, dry etching to form a predetermined pattern of the inorganic film. In this case, the inorganic film IO is extremely thin and has a high selectivity to the material layer 12 during dry etching, so the material layer 12
It is possible to pattern the inorganic film 10 even if the thickness of the inorganic film 10 is small. Next, using this predetermined pattern as a mask, the organic film 9 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, reactive ion etching (R, IE) to form a predetermined pattern made of an organic film. Using this predetermined pattern as a mask, the aluminum film 8 is anisotropically etched by, for example, RIE to form a wiring pattern 13. Of the wiring pattern 13 formed in this way, the wiring portion with a small width is
The width is approximately the same as the diameter of the electron beam 11, and therefore extremely fine wiring 13 can be formed.
しかも、第1図に示すようにこの配線13を形成すべき
領域の無機膜10の表面を電子ビーム11で照射するこ
とにより物質層12を形成し、これをマスクとして無機
膜10、有機膜9及びアルミニウム膜8を順次エツチン
グすることにより配線パターン13を形成しているので
、微細な配線13を容易に形成することができる。Moreover, as shown in FIG. 1, a material layer 12 is formed by irradiating the surface of the inorganic film 10 in a region where the wiring 13 is to be formed with an electron beam 11, and using this as a mask, the inorganic film 10 and the organic film 9 are Since the wiring pattern 13 is formed by sequentially etching the aluminum film 8 and the aluminum film 8, the fine wiring 13 can be easily formed.
この後、無機膜10及び有機膜9をエツチング除去して
、第4図に示すように目的とする半導体集積回路装置を
完成させる。Thereafter, the inorganic film 10 and the organic film 9 are removed by etching to complete the intended semiconductor integrated circuit device as shown in FIG.
以上、本発明者によってなされた発明を前記実施例に基
づき具体的に説明したが、本発明は前記実施例に限定さ
れるものではなく、その要旨を逸脱しない範囲において
種々変形し得ることは勿論である。As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. It is.
例えば、上述の実施例においてはアルミニウムの配線パ
ターン13を形成する場合について説明したが、本発明
は、配線以外の各種の微細パターンを形成する場合にも
適用することができる。また、本発明は、微細パターン
の形成を必要とする各種半導体集積回路装置に適用する
ことができる。For example, in the above-mentioned embodiment, the case where the wiring pattern 13 of aluminum was formed was explained, but the present invention can also be applied to the case where various fine patterns other than wiring are formed. Furthermore, the present invention can be applied to various semiconductor integrated circuit devices that require the formation of fine patterns.
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば。Among the inventions disclosed in this application, the effects obtained by typical inventions will be briefly explained.
下記のとおりである。It is as follows.
すなわち、電子ビームの径と同程度の幅の極めて微細な
パターンを形成することができる。That is, an extremely fine pattern with a width comparable to the diameter of the electron beam can be formed.
=7−=7-
第1図〜第4図は、本発明の一実施例による半導体集積
回路装置の製造方法を工程順に説明するための断面図で
ある。
図中、1・・・半導体基板、4・・・ゲート電極、7・
・・層間絶縁膜、8・・・アルミニウム膜、9・・・有
機膜、10・・無機膜、11・・・電子ビーム、12・
・・物質層、13・・・配線パターンである。
あ
)ソ
第 4 図1 to 4 are cross-sectional views for sequentially explaining a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 1... semiconductor substrate, 4... gate electrode, 7...
...Interlayer insulating film, 8...Aluminum film, 9...Organic film, 10...Inorganic film, 11...Electron beam, 12.
...Material layer, 13... Wiring pattern. A) Figure 4
Claims (1)
ことにより形成される少なくとも炭素を含む物質層をエ
ッチングマスクとして用いるようにしたことを特徴とす
る半導体集積回路装置の製造方法。 2、前記真空中に少なくとも炭素を含むガスが導入され
ていることを特徴とする特許請求の範囲第1項記載の半
導体集積回路装置の製造方法。 3、被エッチング膜上に有機膜及び無機膜を順次形成し
、この無機膜に前記電子ビームを照射することによりこ
の無機膜上に前記物質層を形成するようにしたことを特
徴とする特許請求の範囲第1項又は第2項記載の半導体
集積回路装置の製造方法。[Claims] 1. A semiconductor integrated circuit device characterized in that a material layer containing at least carbon, which is formed by irradiating an electron beam in a vacuum with a relatively low degree of vacuum, is used as an etching mask. manufacturing method. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a gas containing at least carbon is introduced into the vacuum. 3. A patent claim characterized in that an organic film and an inorganic film are sequentially formed on the film to be etched, and the material layer is formed on the inorganic film by irradiating the inorganic film with the electron beam. A method for manufacturing a semiconductor integrated circuit device according to item 1 or 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24965186A JPS63104424A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24965186A JPS63104424A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63104424A true JPS63104424A (en) | 1988-05-09 |
Family
ID=17196190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24965186A Pending JPS63104424A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63104424A (en) |
-
1986
- 1986-10-22 JP JP24965186A patent/JPS63104424A/en active Pending
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