JPS63102329U - - Google Patents
Info
- Publication number
- JPS63102329U JPS63102329U JP19736486U JP19736486U JPS63102329U JP S63102329 U JPS63102329 U JP S63102329U JP 19736486 U JP19736486 U JP 19736486U JP 19736486 U JP19736486 U JP 19736486U JP S63102329 U JPS63102329 U JP S63102329U
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- switch
- circuit
- active discharge
- activated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の実施例の構成を示す回路図、
第２図は従来提案されている遅延回路の構成を示
す回路図である。
１……直流電源、２……スイツチ、３，５……
抵抗、４……コンデンサ、６……ツエナダイオー
ド、７……トランジスタ、８……負荷、９，１１
，１３，１４……抵抗、１０，１２……トランジ
スタ。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention;
FIG. 2 is a circuit diagram showing the configuration of a conventionally proposed delay circuit. 1...DC power supply, 2...Switch, 3, 5...
Resistor, 4... Capacitor, 6... Zener diode, 7... Transistor, 8... Load, 9, 11
, 13, 14...Resistor, 10, 12...Transistor.
Claims (1)
れ、この充電回路にコンデンサが接続され、前記
スイツチのＯＮ操作によつて前記充電回路が作動
して、前記コンデンサが充電されて前記コンデン
サに接続されるスイツチング素子がＯＮとされ、
このスイツチング素子に接続された負荷が前記ス
イツチのＯＮ操作から所定時間後に駆動される遅
延回路において、前記スイツチと前記コンデンサ
間に能動放電回路が接続され、前記スイツチのＯ
ＦＦ操作によつて前記能動放電回路が作動して、
前記コンデンサの電荷が放電されるように構成さ
れてなることを特徴とする遅延回路。 A DC power source is connected to a charging circuit via a switch, a capacitor is connected to this charging circuit, and when the switch is turned on, the charging circuit is activated, and the capacitor is charged and connected to the capacitor. The switching element is turned on,
In a delay circuit in which a load connected to this switching element is driven a predetermined time after the ON operation of the switch, an active discharge circuit is connected between the switch and the capacitor, and an active discharge circuit is connected between the switch and the capacitor.
The active discharge circuit is activated by the FF operation,
A delay circuit characterized in that the delay circuit is configured such that the charge of the capacitor is discharged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19736486U JPS63102329U (en) | 1986-12-24 | 1986-12-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19736486U JPS63102329U (en) | 1986-12-24 | 1986-12-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63102329U true JPS63102329U (en) | 1988-07-04 |
Family
ID=31157029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19736486U Pending JPS63102329U (en) | 1986-12-24 | 1986-12-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63102329U (en) |
-
1986
- 1986-12-24 JP JP19736486U patent/JPS63102329U/ja active Pending