JPS63101936A - Microprogram execution control system - Google Patents

Abstract

PURPOSE:To vary the execution start address of a microprogram in accordance with the order of processing requests by providing the titled system with a register for holding the execution start address and setting up the execution address for the succeeding processing request in the register in accordance with the end of the processing of the current processing request. CONSTITUTION:A microprogram execution address forming circuit 30 outputs a microprogram execution start address set up in the register 15 to a microprogram processing part 31. The processing part 31 reads out a microprogram from the applied execution start address, executes the program, and at the time of ending the processing request, sets up the execution start address of the succeeding processing request in the register 15. Thereby, the execution start addresses of the microprogram can be varied in accordance with the order of the processing requests such that addresses A-C can be set up correspondingly to the 1st-3rd processing requests.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems (Fig. 1) Working example (a) One example Explanation of the configuration (Figure 2) (b) Explanation of the operation of one embodiment (Figures 3, 4, 5, and 6) (c) Explanation of other embodiments Effects of the invention [Summary] In order to make the execution start address of the microprogram variable depending on the order of processing requests, the execution start address of the next processing request is set in a register when the processing of the microprogram processing section is completed in response to the processing request, and In response, the execution address generation circuit outputs the execution start address of the register to the microprogram processing section.

[Industrial application field]

The present invention relates to a microprogram execution control method in which an execution start address of a microprogram can be made variable according to the order of processing requests in an information processing apparatus that processes processing requests by executing microprograms.

Microprogram control methods are widely used in information processing devices. In such microprogram control, a wide variety of processing is required in recent years, and it is required to execute processing by changing the execution start address of the microprogram according to processing requests.

[Conventional technology]

In conventional microprogram control, the execution start address is constant for the same processing request.

Also, if another processing request such as an interrupt occurs while the main routine is being executed in response to a processing request, the main routine is interrupted, the interruption address is saved in a register, and the subroutine corresponding to the other processing request is jumped to. , then return to the interrupt address in the register, execute the main routine, and end the process.

Therefore, in order to make the execution start address of a microprogram variable in response to a processing request, it is necessary to set a plurality of processing requests.

[Problem that the invention seeks to solve]

For example, in DMA (direct memory access) control of two-dimensional data, it is necessary to generate addresses for memory access in response to transfer requests, which are processing requests, but the address generation operation is changed depending on the order of the transfer requests. Therefore, the execution start address of the microprogram must be changed.

When it is necessary to change the execution start address of a microprogram according to the order of processing requests, conventional technology has been able to change the execution start address of a microprogram depending on the order of processing requests. - It is necessary to input the processing requests separately, which not only increases the load on the processing request source but also requires multiple processing request lines, complicating the processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram execution control method that can easily vary the execution start address of a microprogram according to the order of processing requests.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 15 is a register in which the execution start address of the microprogram is set, and 30 is a microprogram execution address generation circuit, which is a microprogram processing unit that generates the execution start address of the register 15 according to a processing request. 31 is a microprogram processing unit that reads and executes a microprogram from a given execution start address, and also stores the execution start address of the next processing request in the register 15 when the processing for the processing request is completed. It is something to set.

[Effect]

In the present invention, when the microprogram processing unit 31 finishes processing a processing request, it stores the execution start address of the next processing request in the register 15. For example, as shown in FIG. The execution start address of the microprogram is set in the order of processing requests, such as address A for the first processing request, address B for the second processing request, address C for the third processing request, and so on. It can be made variable depending on the situation.

Therefore, even when performing complex microprogram control, it can be easily realized using the same processing request.

〔Example〕

(a) Description of the configuration of an embodiment FIG. 2 is a configuration diagram of an embodiment of the present invention, and shows an example applied to a two-channel two-dimensional DMAC (direct access memory control circuit).

In the figure, the same parts as those shown in FIG. 10b is the first register of channel 1, 11 is the X register section, where the width XLR of the area to be accessed is set, lla is the X register of channel O, 11b is the channel The X register 1, 11c, and lid are multiplexers, respectively, for inputting the X registers lla and llb of channel 0.1, and the Y register 12 is set to the vertical width YLR of the area to be accessed. 12a is the Y register of channel O, 12b is the Y register of channel 1, 12c and 12d are multiplexers each for inputting the Y registers 12a and 12b of channel O1l, and 13 is an address. This is a register section in which the first real address of the area to be accessed is set. 13a is an address register for channel 0, 13b is an address register for channel 1, 13c and 13d are multiplexers, and each address register 13a ,1
3b is an input, and 13e is a multiplexer for selecting the output of address registers 13a and 13b.

Reference numeral 14 denotes an operation mode register, which is used to hold the operation mode specified by the CPU (address update mode, data transfer unit, read/write, etc.). 15 is the aforementioned program register which holds the microprogram execution start address for each channel, and includes a program register 15a for channel O and a program register 15b for channel 1. It has the following.

30 is the aforementioned microprogram execution address generation circuit (hereinafter referred to as CBG), which generates the DMA transfer request signal DR.
When receiving QO, DRQI, operation mode register 1
4a, 14b and the values of the program registers 15a, 15b to give a microprogram execution start address to a sequence control circuit (to be described later); 31 is a sequence control circuit as the microprogram processing section mentioned above, which starts execution from CBG 30; According to the address, register update instructions and memory access instructions are given to the register update control circuit and memory interface control circuit, which will be described later, under microprogram control.
A sequencer 31a that generates successive addresses according to an internal program counter based on an execution start address from , a program memory (ROM) 3lb that stores a microprogram for two-dimensional address generation,
It has a pipeline register 31c that distributes the contents (instructions, data) read from the OM 31b to the register update control circuit 32, sequencer 31a, program registers 15a, 15b, memory interface control circuit, etc.; Register update control circuit (hereinafter referred to as R)
OP), and registers 10a, 10b, lla, llb, 12a,
Take the contents of 12b, 13a, 13b, add and subtract,
Registers lla, llb, 12a, 12b, 13a, 1
3b and registers lla, 11b, 1
The contents of 2a and 12b are determined and the sequence control circuit 31
This is to notify the sequencer 31a. Note that these 30, 31, and 32 constitute the two-dimensional address generation circuit 3 of DMACl.

Reference numeral 4 denotes a memory interface control circuit (hereinafter referred to as MIF), which performs memory access control according to instructions from the sequence control circuit 31 (pipeline register 31C). For example, it sends a transfer request R to a transfer request source.
It issues a response ACK to the EQ, a transfer end DTC, a read/write instruction R/W to the memory 2, and a read/write timing TR/W.

In this embodiment, since data having a two-dimensional structure called image data is transferred by DMA, the address update control changes the address update amount after one transfer process, such as byte or word, depending on the position of the data to be transferred. It becomes complicated, and the order of image data transfer is correct (Z type)
This is done by microprogram control so that it can change depending on the access, rotational (N-type) access, inversion (inverted Z-type) access, etc.

Address update processing by the microprogram is performed each time a transfer request DRQO or DRQI arrives, and is divided into bytes, words, etc. The execution order of the divided microprograms is changed according to the order of transfer requests so that desired address update processing can be performed.

That is, the microprogram is normally in a state of waiting for a transfer request, and when it receives a transfer request, it partially executes the processing program for the requested channel, and after one transfer is completed, it returns to the state of waiting for a transfer request. Control takes place.

(b) Description of operation of one embodiment FIG. 3 is a system configuration diagram of an embodiment according to the present invention.

In the figure, the same components as those shown in FIGS. 1 and 2 are indicated by the same symbols, and 1 is DMAC.

2 is a memory, 5 is a processor, which is composed of a microprocessor, and 6 is a read/write controller (hereinafter referred to as RWC), which processes the image data obtained by DMA transfer and performs DMA transfer. What writes to memory 2, A-BUS is an address bus, and D-BU
S is a data bus.

In this system, the processor 5 sets the operation mode, the screen width WDROSWDR1, the access area width XLRO1XLR1, the height YLRO, YLRI, and the first real address ADRO1ADR1 in DMACl, and
After starting C6, if RWC6 is read, transfer request REQO.

If it is a write, DM is sent by issuing a transfer request REQI.
ACl accesses memory 2 with the real address of the generated two-dimensional data by stealing the cycle, and performs read/write operations.
Write instruction R/W, memory 2 at that timing TR/W
The RWC 6 and the memory 2 exchange data by accessing the RWC 6 and the memory 2.

4 and 5 are process flow diagrams of one embodiment of the present invention, showing the structure of a Z-type access microprogram stored in the program memory 31b. FIG. 4 shows a microprogram starting from address A, 5(A) shows a microprogram starting from address B, and FIG. 5(B) shows a microprogram starting from address C. This program is prepared in the program memory 31b for each channel.

Hereinafter, when data having a two-dimensional structure stored in the one-dimensional memory 2 in FIG. Transfers such as a' to f' in which channel O is used for reading data and channel I is used for writing data will be explained.

Therefore, the processor 5 issues a read instruction, a Z-type address update mode instruction, and a byte transfer instruction to the DMACl mode register 14a via the data bus D-BUS, and a write mode instruction and Z-type address update mode instruction to the mode register 14b. , issues a byte transfer instruction. Also, register 1
0a and 10b have the screen width WDRO=WDR1-r5
J, X registers lla and llb have the horizontal width XLRO-XLR1=r3J of the transfer data size, and Y registers 12a and 12b have the vertical width YLRO of the transfer data size.
=YLR1-r2J, the address register 13a has the transfer source start address ADRO="6", and the address register 13b has the transfer destination start address ADR1=r2.
Set 0J.

After performing the above settings, the processor 1 activates the RWC 6.

RWC6 notifies DMACl of DRQO and requests data read.

In DMACl, the CBG 30 determines the microprogram execution start address from the address update mode of the mode register 14a, and outputs the microprogram execution address to the sequencer 31a. In this case, because of the Z-type address update mode, address A is designated as the execution address, and the process shown in FIG. 4 is started.

(2) The sequencer 31a loads address A into the program counter and reads the microprogram at the corresponding address from the program memory 31b.

This microprogram indicates the start of memory access,
The pipeline register 31C, which performs the decoder function, sends an access start instruction to the MIF4 to the multiplexer 1.
3e is instructed to output the content ADRO of the address register 13a, and the ROP32 is instructed to update the content of the X register 1la (llb), (XLR-1)→XLR.

As a result, the real address of the address register 13a of channel 0 is output, a read instruction and read timing are given from the MIF 4 to the memory 2, and further,
ROP32 takes in the content XLRO of the X register 11a, performs the operation (XLRO-1), and sends the multiplexer
Update the X register lla to (XLRO-1) via lc.

- By incrementing the program counter of the sequencer 31a, the next address is given to the program memory 31b, and XLR= is sent from the pipeline register 31c to the ROP32.
1, that is, an instruction is given to determine whether the next transfer data is the final data in the horizontal direction.

The ROP 32 takes in the content XLRO of the X register lla, determines whether XLRO=1, and notifies the sequencer 31a.

(2) If XLRO≠1, the sequencer 31a gives the next address to the program memory 31b. As a result, the pipeline register 31c instructs the sequencer 31a to determine whether the MIF 4 has notified the end of memory access.

The sequencer 31a waits for a memory access notification, and upon receiving the memory access notification, increments the program counter and reads the program memory 31b.

This content is an address update instruction, and (ADH+1)-AD
Instruct R.

ROP32 is the content ADRO of address register 13a.
is fetched, performs the operation of (ADRO+1), and sets the address register 13a to (ADRO+1) via the multiplexer 13C.
Update to RO+1).

Furthermore, the sequencer 31a increments the program counter and reads the program memory 31b.

This content indicates update of the program register, and the execution start address A of the next transfer request DRQO in FIG. 4 is set in the program register 15a of channel O from the pipeline register 31c.

Next, the sequencer 31a increments the program counter and reads the program memory 31b. Then, the pipeline register 31c gives the sequencer 31a a branch instruction to the address of the CBG 30, and the sequencer 31a
Branch to the address of BG30. After outputting the program execution address for one transfer request, CBG30 outputs the non-operation (Non-operation) within the microprogram.
Since the address where the 0operation) instruction is stored is output, the sequencer 31a enters a non-operation state due to the output of the program memory 31b, completes address update processing for one transfer request, and waits for a transfer request.

■ On the other hand, in step ■, the sequencer 31a
When notified that =1, the next transfer data is data in the next line (d in the figure, so a branch jump is made) and the program counter is incremented by the jump amount. This reads the program memory 31b.

This is a determination instruction for YLR=1 that determines whether the next transfer data is the final data in the vertical direction, so this determination instruction is given to the ROP 32 via the pipeline register 31C.

The ROP32 takes in the contents of the Y register 12a and stores the contents of the Y register 12a.
It is determined whether LRO=1 or not, and the sequencer 31a is notified.

(2) If YLRO≠1, the sequencer 3'1a increments the program counter, reads the contents one after another, and executes them. That is, as in step (2), a memory access end determination instruction is executed, an address update instruction is executed, and a program register update instruction is executed, and the microprogram execution start address of the next transfer request is stored in the program register 15a. Set address B as . Next, C.B.G.
Executes a branch instruction, enters a non-operation state,
The process ends in the same way as above.

■ On the other hand, in step ■, the sequencer 31a
When notified that O=1, the next transfer data is the final data in the vertical direction, so it jumps, increments the program counter by the jump amount, reads out the program memory 31b, and executes it.

That is, in the same way as in steps ① and ②, a memory access end determination instruction is executed, an address update instruction is executed, a program register update instruction is executed, and the microprogram execution for the next transfer request is written to the program register 15a. Set address C as the starting address. Next, CBG
Executes a branch instruction, enters a non-operation state,
The process ends in the same way as above.

The CBG 30 gives a microprogram execution start address to the sequencer 31a every time a DRQO arrives, and causes the sequencer 31a to execute the microprogram. That is, address A is given to the first DRQO (determined by the DRQ immediately after setting in the mode register), and the contents of the program register 15a are given as the program execution address to subsequent DRQOs.

Therefore, when address A is given as the program execution start address, the sequence control circuit 31 executes the process shown in FIG. 4, and when address B is given as the program execution start address, the sequence control circuit 31 executes the process shown in FIG. given and fifth
The process shown in Figure (B) is executed.

That is, when address B is given, as shown in FIG. 5(A), from the program memory 31b, step
Instruction to start accessing IF4, address register 13a
(13b) output instruction is sent to Y register 12a (12b)
The content update instruction (YLR-1)-YLRl is further output, as is the initial value instruction for the X register 1la (1lb). As a result, the real address of the address register 13a of channel O, the read instruction from the MIF 4, and the read timing are output.
a The contents of (channel 0) are imported into YLRO, and (Y
LRO-1), updates the Y register 12a to (YLRO-1) via the multiplexer 12G, and
The register 12a is updated to the initial value ("3" in FIG. 6).

Thereafter, the contents of the program memory 31b are successively read out and executed according to the progress of the program counter.

That is, the memory access end determination instruction is executed, then the address update instruction is executed, the program register update instruction is executed, and then the CBG address branch instruction is executed, and the process ends.

At this time, the address update is performed in the address register 13a (1
The content of 3b) ADH is ADR+ (WDR-XLR+1
), and for example, in FIG. 6, the address of data d from data C is updated, and the program register update is updated to address A as the execution start address of the next transfer request.

Also, when given from address C, as shown in FIG. 5(B), from the program memory 31b, M
Instruction to start accessing IF4, address register 13a
The output instruction is the instruction to update the contents of the X register 11a (llb) (XLR-1) -
The content update command (YLR-1)-YLR of b) is output and executed in the same manner.

Thereafter, as the program counter advances, the contents of the program memory 31b are successively read out and executed. That is, the memory access end determination instruction, then the transfer end notification instruction instruction to the MIF 4, and the CBG address branch instruction are executed, and the process ends.

Similarly, when a write transfer request DRQ1 for channel 1 arrives, the same operation is performed in registers 10b and l for channel 1.
lb, 12b, 13b, 14b.

15b.

Therefore, in the example shown in FIG. 6, address A is given as the execution address by the first transfer request DRQO, steps ■, ■, and ■ in FIG. 4 are performed, and the address "5" of data a is
'', the width XLRO is updated (r3J-r2J), the next address "6" is calculated, and the execution address A is set for the next transfer request to the program register 15a.

Thereafter, the operation is restarted according to the execution address of the program register 15a, and in the next transfer request DRQO, address A is given as the execution start address, and step ① in FIG.
, ■, ■, ■ are performed, outputting address "6" of data b, updating width XLRO (r2J-NJ), calculating next address "7", execution start address B for next transfer request of program register 15a. The address is sent, and in the third transfer request DRQO, address B is given as the execution start address. Through the process shown in FIG. Update height YLRO (r2J - "1"), width XLRO for transfer
is updated to the initial value "3", and then the address of the next transfer data d is calculated as (ADR+ (WDR-XLR+1)), that is, (7+5-3+1)=10, and the execution start address A for the next transfer request is calculated. Do a set.

For the fourth transfer request DRQO, step ■,
Steps ■, ■ are executed, and steps ■, ■, ■, ■ are executed for the fifth transfer request DRQO, and steps ■, ■, ■, ■ are executed for the sixth transfer request DRQO, and as shown in FIG. 5(B) processing is executed.

Therefore, by setting data to registers 10.11 and 12.13, any region in two-dimensional space, XLR, YLR
Data in the area defined by can be transferred by DMA.

RWC6 uses channel O and transfers read DMA transfer from memory 2 to R with transfer request DRQO to DMA C1.
WC6, then use channel 1 and transfer request D
If RQ1 causes DMACl to perform write data transfer alternately from RWC6 to memory 2, as shown in FIG. D to a゛, b′, C′, d′, e′, f゛
MA transfer is possible. That is, two-dimensional data transfer is possible with one activation of the processor 5.

In addition, in this embodiment, since the address update mode can be set, not only the Z-type mode mentioned above but also the N-type mode etc. can be selected, and various image data processing such as rotation and inversion of image data can be performed by DMA transfer. It becomes possible.

Moreover, the series of address update processing according to the address update mode is performed as shown in FIGS. 4 and 5 (even if the processing program is divided and the execution order is undefined, after receiving the transfer request, the processing program is partially executed, After the transfer process is completed, the restart address for the next transfer request can be known by the program counter 15, and the execution start address of the microprogram is changed according to the order of the same transfer request, thereby performing complex address update processing. Can be done.

Furthermore, this can be made independent of channel 0.1, and even if the execution start address is changed, two sequence control circuits (microprogram processing units) 31 can be used smoothly.
Channel processing becomes possible.

(c) Description of other embodiments In the embodiments described above, the application of a two-channel DMAC was explained, but it may also be a one-channel one, and the address update mode is not limited to one type, but may have multiple types. Alternatively, the RWC 6 may not perform read/write alternately, but may perform read multiple times and then write multiple times.

Furthermore, although the microprogram processing has been described with respect to address update processing in the DMAC, the present invention is not limited to this and can be applied to other processing.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, a register is provided to hold the execution start address, and the execution address of the next processing request is set according to the completion of processing for the processing request. This has the effect that the execution start address of the microprogram can be made variable according to the requirements, and the effect that complex processing can be executed in various ways in the order of the same processing request is achieved, so that the microprogram processing can be executed in a variety of ways.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the principle of the present invention, Figure 2 is a configuration diagram of an embodiment of the invention, Figure 3 is a diagram of a system configuration of an embodiment of the invention, and Figures 4 and 5 are diagrams of the invention. Process Flowchart of an Embodiment FIG. 6 is an explanatory diagram of the operation of an embodiment of the present invention. In the figure, 1--DMAC, 2-memory, 3--two-dimensional address generation circuit, 15--program register, 30--microprogram execution address generation circuit, 31--sequence control circuit (microprogram processing section).

Claims (1)

[Claims] A microprogram processing unit (31) that reads and executes a microprogram from a given execution start address; a register (15) that holds the execution start address of the microprogram; It has an execution address generation circuit (30) that outputs the execution start address of the register (15) to the microprogram processing section (31), and when the processing of the microprogram processing section (31) is completed, the next execution address is output. The execution start address of the processing request is set in the register (1
5) A microprogram execution control method characterized in that the execution start address is made variable according to the order of the processing requests by setting the above.