JPS63100491A - Mask pattern generation circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data write control circuit to a memory that realizes a transfer/copy function in bitmap CRT control, and in particular to a bit-by-bit write control circuit for a memory with a word boundary. The present invention relates to a mask circuit.

[Conventional technology]

Conventionally, this type of mask pattern generation circuit has a method of storing mask patterns corresponding to leading edge/trailing edge dot addresses and leading edge/trailing edge OS writing control signals in a read-only memory (hereinafter referred to as ROM). The ROM is read out using these leading edge/trailing edge dot addresses and leading edge/trailing edge write control signals as addresses to generate a mask pattern.

[Problem that the invention seeks to solve]

The above-mentioned conventional mask pattern generation circuit uses a ROM and therefore has a large number of elements, and has the disadvantage that the number of elements required for this control is also large.

[Means for solving problems]

The mask pattern generation circuit of the present invention has a leading edge dot address representing the position of the first written bit as an address within a word where the bit is located, and a position txt-to of the last written bit as an address within the word where the bit is located. Note that the mask pattern corresponding to the trailing edge dot address expressed as , upper/lower patterns are determined with the corresponding dot address as the boundary. Solution af! a leading edge mask generator that generates a leading edge mask pattern from a leading edge mask pattern; a trailing edge dot address decoder that decodes a trailing edge dot address; and a trailing edge mask generator that generates a trailing edge mask pattern from the decoding result of the decoder. It consists of a mask selector that allows or prohibits leading edge and trailing mask patterns and performs compositing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, in one embodiment of the present invention, the number of bits of the mask pattern is 16 bits.

Register l is a 4-bit register that stores a leading edge dot address (hereinafter referred to as 5DA). Decoder 3 is
This is a decoder that decodes 4 bits of 5DA=i output from register 1. A mask pattern generator sFi generates a leading edge mask pattern from the decoding result of the decoder 3.

The detailed configuration of the decoder 3 and the mask pattern generator 5 is shown in FIG. 2, and the relationship between the SDA, the decoder 3, and the mask pattern generator 5 is shown in FIG. Decoder 3 is 5DA
When 4 bits are decoded, only 1 bit is 1 as shown in Figure 5.
FbitQ~F outputs a pattern that becomes @01 when the bit higher than a certain bit is 0°, and when the bit itself is 100, the bit lower than that bit is @01. Set all bits to “0°. In this way, a leading edge mask pattern is generated from SDA.

In FIG. 1, register 7 is a 4-bit register that stores a trailing edge dot address (hereinafter referred to as EDA).

4-bit E output from decoder 9- and register 7
DAt - decoder for decoding. A mask pattern generator 11 generates a trailing edge mask pattern from the output result of the decoder 9.

The detailed configuration of the decoder 9 and mask pattern generator 11 is shown in FIG. 3, and the relationship between the EDA and the decoder 9 is shown in FIG. The decoder 9 outputs a pattern in which only one bit becomes "θ" as shown in FIG. 6 when the 4 bits of El)A are viewed as t@. For EbitQ to F, when a bit lower than a certain bit is 0'', that bit is ``0''.If the bit itself is @0'', all bits higher than that bit are Set it to “0”. Like this KLEDA
Generate a trailing edge mask pattern from.

The mask selector 15 of FIG. 1 allows, disallows, and combines leading edge/trailing edge mask patterns.

In FIG. 4, leading edge mask selectors 15-IA to 15
-16A allows the leading edge mask pattern (Fb it ) when the leading edge mask enable signal (FOL) is valid, and disables it when it is invalid. Also, Gochang Mask Permit No. F6 (EUL)
When is enabled, trailing edge mask pattern (Ebit) t
- Allow, and prohibit when disabled.

The mask synthesizer 15-IC-15-16C synthesizes the leading edge mask pattern and the trailing edge mask pattern. Leading edge mask enable signal (FOL) and trailing edge mask enable signal (EOL)
operate independently, so all mask patterns can be displayed in four states: leading edge/trailing edge masking allowed, leading edge masking only, trailing edge masking only, and leading edge/trailing edge masking prohibited, as shown in Figure 7. Occur.

Next, an embodiment of the present invention in which the leading edge mask generator 5 and the trailing edge mask generator are improved will be described in detail below. Here, the AND gate input of the mask pattern generator is assumed to be performed by a maximum of four people. Decoder 3 is 5DA
When 4 bits are decoded, a pattern in which only 1 bit becomes @0@ is output, as shown in the output of the leading edge dot address decoder 3 in FIG. Using this output result, the leading edge mask generator 5 generates a leading edge mask pattern. This pattern shows that when 5DA3~0 is expressed in hexadecimal, SDA is 0.
When M, the leading edge mask generator 50 output L1 is all @l゛, and when SDA is IH, the output is FbitO is 10''
The other outputs are @1''. In this way, when SDA is FM, one output has a pattern in which FbitF is 11'' and other outputs are @θ''. This situation is shown in FIG.

ζHere, the AND gate uses a multi-input gate as shown in FIG. 8, and has only three stages at most.

In FIG. 1, the register 7 is connected to the trailing edge dot L/S (
This is a 4-bit register that stores the data (EDA). The decoder 9 receives the 4-bit ED output from the register 7.
This is a decoder that decodes A.

The detailed configuration of the decoder 7 and the trailing edge mask generator 11 is described in the ninth section.
As shown in the figure. The input of the EDA, decoder 7, and AND gate of the trailing edge mask generator requires a maximum of four people. When the decoder 7 decodes the 4 bits of EDA, it outputs a pattern in which only 1 bit is @0'', as shown in the output of the trailing edge dot address decoder in FIG. Generator 11 generates a trailing edge mask pattern.This pattern is expressed by trailing edge mask generator 1 when EDA to FHO when EDA3SO is expressed in hexadecimal
1 outputs are all “l”, and when EDA is EH, EbitF is “O” and all other outputs are @l”
becomes. In this way, E D A: OE O+4O
N#O out cover, Eb l t Oka" 1 "' T Others are 10". This situation is seen in the 6th
As shown in the figure. In this case, the AND gate uses a multi-input gate as shown in FIG. 9, and has only three stages at maximum.

The mask selector 15 of FIG. 1 allows, inhibits, and combines leading edge/trailing edge mask patterns.

In FIG. 4, leading edge mask selectors 15-IA to 15-
16A, when the leading edge mask enable signal (FOL) is enabled,
Enables leading edge mask pattern (Fbit) and disables it when disabled. Also, when the trailing edge mask permission signal (]!;OL) is valid, the trailing edge mask pattern (Ebtt) is enabled,
This is prohibited when disabled.

The mask synthesizer 15-IC 15-16c synthesizes the leading edge mask pattern and the trailing edge mask pattern. Leading edge mask enable signal (FOL) and trailing edge mask enable signal (EOL)
operate independently, so all mask patterns are generated in four states: leading edge/trailing edge masking enabled, leading edge masking only, trailing edge masking only, and leading edge/trailing edge masking prohibited, as shown in Figure 7. do.

By changing the connection of the AND gates constituting the leading edge and trailing edge mask generators in this way, the time for determining a striped pattern can be shortened.

〔Effect of the invention〕

As explained above, the present invention uses logic gates to
(In addition to generating a trailing edge mask pattern), the mask pattern can be generated using a small-scale logic element.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing a detailed configuration of the leading edge dot address decoder 3 and the leading edge mask generator 5 shown in FIG.
40 is a diagram showing the detailed configuration of the i screen selector 15 shown in FIG. 1. FIG. 5 is a diagram for explaining the relationship between the leading edge mask pattern, the leading edge dot address decoder 3, and the leading edge mask pattern, and FIG. A diagram for explaining the relationship between the decoder 9 and the trailing edge mask pattern, FIG. 7 is a diagram showing how a mask pattern is generated within a word, and FIG. 8 is a diagram showing a modification of the configuration of FIG. 2. This figure and FIG. 9 are views showing a modification of the configuration of FIG. 3. In the figure, 1... register, 2...
・Leading edge dot, door address, 3...Leading edge dot address decoder, 3-1.3-2...decoder,
3-3... Inverter, 4... Leading edge dot address decode output, 5... Leading edge mask generator 15-1 to 5-14... Mask pattern generator, 6·°...- Leading edge mask pattern, 7...
...Register, 8... Trailing edge dot address,
9... Trailing edge dot address decoder, 9-1.
9-2... Decoder, 9-3... Inverter, 10... Trailing edge dot address decoder, 11... Edge mask generator, 11 -1 to 11
-14...Mask pattern generator, 12...Kawa/Shunen mask pattern, 13...Leading edge mask permission signal (FOL), 14...Mask permission afterward Signal (EOL), 15°°. Pa mask selector, 15-IA to 15-16A...Pa°° cocoon edge mask selector, 15-IB to 15-16B.
...edge mask selector, 15-1 to 15-IC
6C...-vxreoforma, 16... Indicates mask pattern output. Figure 2 l-÷-FbltF 3rd depression Figure 4 Figure g Figure q

Claims (1)

[Scope of Claims] A mask pattern generation circuit in a CRT control device, comprising a leading edge dot address decoding means for decoding a leading edge dot address, and a leading edge mask for generating a leading edge mask pattern from the output result of the decoding means. generating means; trailing edge dot address decoding means for decoding a trailing edge dot address; trailing edge mask generating means for generating a trailing edge mask pattern from the output result of the decoding means; and permission for leading edge and trailing edge mask patterns. 1. A mask pattern generation circuit comprising: a mask selection means for inhibiting or inhibiting a pattern, and a mask selection means for performing synthesis.